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Side by Side Diff: src/s390/macro-assembler-s390.h

Issue 2072863003: S390: Enable unaligned accesses and character preloading in regexp. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Change comment on load reverse Created 4 years, 4 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_S390_MACRO_ASSEMBLER_S390_H_ 5 #ifndef V8_S390_MACRO_ASSEMBLER_S390_H_
6 #define V8_S390_MACRO_ASSEMBLER_S390_H_ 6 #define V8_S390_MACRO_ASSEMBLER_S390_H_
7 7
8 #include "src/assembler.h" 8 #include "src/assembler.h"
9 #include "src/bailout-reason.h" 9 #include "src/bailout-reason.h"
10 #include "src/frames.h" 10 #include "src/frames.h"
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105 #define SubP_RRR sgrk 105 #define SubP_RRR sgrk
106 #define SubLogicalP_RRR slgrk 106 #define SubLogicalP_RRR slgrk
107 #define AndP_RRR ngrk 107 #define AndP_RRR ngrk
108 #define OrP_RRR ogrk 108 #define OrP_RRR ogrk
109 #define XorP_RRR xgrk 109 #define XorP_RRR xgrk
110 110
111 // Load / Store 111 // Load / Store
112 #define LoadRR lgr 112 #define LoadRR lgr
113 #define LoadAndTestRR ltgr 113 #define LoadAndTestRR ltgr
114 #define LoadImmP lghi 114 #define LoadImmP lghi
115 #define LoadLogicalHalfWordP llgh
116 115
117 // Compare 116 // Compare
118 #define CmpPH cghi 117 #define CmpPH cghi
119 #define CmpLogicalPW clgfi 118 #define CmpLogicalPW clgfi
120 119
121 // Shifts 120 // Shifts
122 #define ShiftLeftP sllg 121 #define ShiftLeftP sllg
123 #define ShiftRightP srlg 122 #define ShiftRightP srlg
124 #define ShiftLeftArithP slag 123 #define ShiftLeftArithP slag
125 #define ShiftRightArithP srag 124 #define ShiftRightArithP srag
(...skipping 17 matching lines...) Expand all
143 #define SubP_RRR srk 142 #define SubP_RRR srk
144 #define SubLogicalP_RRR slrk 143 #define SubLogicalP_RRR slrk
145 #define AndP_RRR nrk 144 #define AndP_RRR nrk
146 #define OrP_RRR ork 145 #define OrP_RRR ork
147 #define XorP_RRR xrk 146 #define XorP_RRR xrk
148 147
149 // Load / Store 148 // Load / Store
150 #define LoadRR lr 149 #define LoadRR lr
151 #define LoadAndTestRR ltr 150 #define LoadAndTestRR ltr
152 #define LoadImmP lhi 151 #define LoadImmP lhi
153 #define LoadLogicalHalfWordP llh
154 152
155 // Compare 153 // Compare
156 #define CmpPH chi 154 #define CmpPH chi
157 #define CmpLogicalPW clfi 155 #define CmpLogicalPW clfi
158 156
159 // Shifts 157 // Shifts
160 #define ShiftLeftP ShiftLeft 158 #define ShiftLeftP ShiftLeft
161 #define ShiftRightP ShiftRight 159 #define ShiftRightP ShiftRight
162 #define ShiftLeftArithP ShiftLeftArith 160 #define ShiftLeftArithP ShiftLeftArith
163 #define ShiftRightArithP ShiftRightArith 161 #define ShiftRightArithP ShiftRightArith
(...skipping 162 matching lines...) Expand 10 before | Expand all | Expand 10 after
326 // Compare Logical Byte (CLI/CLIY) 324 // Compare Logical Byte (CLI/CLIY)
327 void CmpLogicalByte(const MemOperand& mem, const Operand& imm); 325 void CmpLogicalByte(const MemOperand& mem, const Operand& imm);
328 326
329 // Load 32bit 327 // Load 32bit
330 void Load(Register dst, const MemOperand& opnd); 328 void Load(Register dst, const MemOperand& opnd);
331 void Load(Register dst, const Operand& opnd); 329 void Load(Register dst, const Operand& opnd);
332 void LoadW(Register dst, const MemOperand& opnd, Register scratch = no_reg); 330 void LoadW(Register dst, const MemOperand& opnd, Register scratch = no_reg);
333 void LoadW(Register dst, Register src); 331 void LoadW(Register dst, Register src);
334 void LoadlW(Register dst, const MemOperand& opnd, Register scratch = no_reg); 332 void LoadlW(Register dst, const MemOperand& opnd, Register scratch = no_reg);
335 void LoadlW(Register dst, Register src); 333 void LoadlW(Register dst, Register src);
334 void LoadLogicalHalfWordP(Register dst, const MemOperand& opnd);
335 void LoadLogicalHalfWordP(Register dst, Register src);
336 void LoadB(Register dst, const MemOperand& opnd); 336 void LoadB(Register dst, const MemOperand& opnd);
337 void LoadB(Register dst, Register src); 337 void LoadB(Register dst, Register src);
338 void LoadlB(Register dst, const MemOperand& opnd); 338 void LoadlB(Register dst, const MemOperand& opnd);
339 339
340 void LoadLogicalReversedWordP(Register dst, const MemOperand& opnd);
341 void LoadLogicalReversedHalfWordP(Register dst, const MemOperand& opnd);
342
340 // Load And Test 343 // Load And Test
341 void LoadAndTest32(Register dst, Register src); 344 void LoadAndTest32(Register dst, Register src);
342 void LoadAndTestP_ExtendSrc(Register dst, Register src); 345 void LoadAndTestP_ExtendSrc(Register dst, Register src);
343 void LoadAndTestP(Register dst, Register src); 346 void LoadAndTestP(Register dst, Register src);
344 347
345 void LoadAndTest32(Register dst, const MemOperand& opnd); 348 void LoadAndTest32(Register dst, const MemOperand& opnd);
346 void LoadAndTestP(Register dst, const MemOperand& opnd); 349 void LoadAndTestP(Register dst, const MemOperand& opnd);
347 350
348 // Load Floating Point 351 // Load Floating Point
349 void LoadDouble(DoubleRegister dst, const MemOperand& opnd); 352 void LoadDouble(DoubleRegister dst, const MemOperand& opnd);
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1906 inline MemOperand NativeContextMemOperand() { 1909 inline MemOperand NativeContextMemOperand() {
1907 return ContextMemOperand(cp, Context::NATIVE_CONTEXT_INDEX); 1910 return ContextMemOperand(cp, Context::NATIVE_CONTEXT_INDEX);
1908 } 1911 }
1909 1912
1910 #define ACCESS_MASM(masm) masm-> 1913 #define ACCESS_MASM(masm) masm->
1911 1914
1912 } // namespace internal 1915 } // namespace internal
1913 } // namespace v8 1916 } // namespace v8
1914 1917
1915 #endif // V8_S390_MACRO_ASSEMBLER_S390_H_ 1918 #endif // V8_S390_MACRO_ASSEMBLER_S390_H_
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