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| 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 | 4 |
| 5 #include "vm/flow_graph_allocator.h" | 5 #include "vm/flow_graph_allocator.h" |
| 6 | 6 |
| 7 #include "vm/bit_vector.h" | 7 #include "vm/bit_vector.h" |
| 8 #include "vm/intermediate_language.h" | 8 #include "vm/intermediate_language.h" |
| 9 #include "vm/il_printer.h" | 9 #include "vm/il_printer.h" |
| 10 #include "vm/flow_graph.h" | 10 #include "vm/flow_graph.h" |
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| 434 blocking_ranges[loc.register_code()]->AddUseInterval(from, to); | 434 blocking_ranges[loc.register_code()]->AddUseInterval(from, to); |
| 435 } | 435 } |
| 436 | 436 |
| 437 | 437 |
| 438 // Block location from the start of the instruction to its end. | 438 // Block location from the start of the instruction to its end. |
| 439 void FlowGraphAllocator::BlockLocation(Location loc, | 439 void FlowGraphAllocator::BlockLocation(Location loc, |
| 440 intptr_t from, | 440 intptr_t from, |
| 441 intptr_t to) { | 441 intptr_t to) { |
| 442 if (loc.IsRegister()) { | 442 if (loc.IsRegister()) { |
| 443 BlockRegisterLocation(loc, from, to, blocked_cpu_registers_, cpu_regs_); | 443 BlockRegisterLocation(loc, from, to, blocked_cpu_registers_, cpu_regs_); |
| 444 #if defined(TARGET_ARCH_DBC) |
| 445 last_used_register_ = Utils::Maximum(last_used_register_, |
| 446 loc.register_code()); |
| 447 #endif |
| 444 } else if (loc.IsFpuRegister()) { | 448 } else if (loc.IsFpuRegister()) { |
| 445 BlockRegisterLocation(loc, from, to, blocked_fpu_registers_, fpu_regs_); | 449 BlockRegisterLocation(loc, from, to, blocked_fpu_registers_, fpu_regs_); |
| 446 } else { | 450 } else { |
| 447 UNREACHABLE(); | 451 UNREACHABLE(); |
| 448 } | 452 } |
| 449 } | 453 } |
| 450 | 454 |
| 451 | 455 |
| 452 void LiveRange::Print() { | 456 void LiveRange::Print() { |
| 453 if (first_use_interval() == NULL) { | 457 if (first_use_interval() == NULL) { |
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| 2735 for (intptr_t reg = 0; reg < number_of_registers; reg++) { | 2739 for (intptr_t reg = 0; reg < number_of_registers; reg++) { |
| 2736 blocked_registers_[reg] = blocked_registers[reg]; | 2740 blocked_registers_[reg] = blocked_registers[reg]; |
| 2737 ASSERT(registers_[reg]->is_empty()); | 2741 ASSERT(registers_[reg]->is_empty()); |
| 2738 | 2742 |
| 2739 LiveRange* range = blocking_ranges[reg]; | 2743 LiveRange* range = blocking_ranges[reg]; |
| 2740 if (range != NULL) { | 2744 if (range != NULL) { |
| 2741 range->finger()->Initialize(range); | 2745 range->finger()->Initialize(range); |
| 2742 registers_[reg]->Add(range); | 2746 registers_[reg]->Add(range); |
| 2743 } | 2747 } |
| 2744 } | 2748 } |
| 2745 | |
| 2746 #if defined(TARGET_ARCH_DBC) | |
| 2747 last_used_register_ = -1; | |
| 2748 #endif | |
| 2749 } | 2749 } |
| 2750 | 2750 |
| 2751 | 2751 |
| 2752 void FlowGraphAllocator::AllocateUnallocatedRanges() { | 2752 void FlowGraphAllocator::AllocateUnallocatedRanges() { |
| 2753 #if defined(DEBUG) | 2753 #if defined(DEBUG) |
| 2754 ASSERT(UnallocatedIsSorted()); | 2754 ASSERT(UnallocatedIsSorted()); |
| 2755 #endif | 2755 #endif |
| 2756 | 2756 |
| 2757 while (!unallocated_.is_empty()) { | 2757 while (!unallocated_.is_empty()) { |
| 2758 LiveRange* range = unallocated_.RemoveLast(); | 2758 LiveRange* range = unallocated_.RemoveLast(); |
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| 3003 | 3003 |
| 3004 void FlowGraphAllocator::AllocateRegisters() { | 3004 void FlowGraphAllocator::AllocateRegisters() { |
| 3005 CollectRepresentations(); | 3005 CollectRepresentations(); |
| 3006 | 3006 |
| 3007 liveness_.Analyze(); | 3007 liveness_.Analyze(); |
| 3008 | 3008 |
| 3009 NumberInstructions(); | 3009 NumberInstructions(); |
| 3010 | 3010 |
| 3011 DiscoverLoops(); | 3011 DiscoverLoops(); |
| 3012 | 3012 |
| 3013 #if defined(TARGET_ARCH_DBC) |
| 3014 last_used_register_ = -1; |
| 3015 #endif |
| 3016 |
| 3013 BuildLiveRanges(); | 3017 BuildLiveRanges(); |
| 3014 | 3018 |
| 3015 if (FLAG_print_ssa_liveranges) { | 3019 if (FLAG_print_ssa_liveranges) { |
| 3016 const Function& function = flow_graph_.function(); | 3020 const Function& function = flow_graph_.function(); |
| 3017 THR_Print("-- [before ssa allocator] ranges [%s] ---------\n", | 3021 THR_Print("-- [before ssa allocator] ranges [%s] ---------\n", |
| 3018 function.ToFullyQualifiedCString()); | 3022 function.ToFullyQualifiedCString()); |
| 3019 PrintLiveRanges(); | 3023 PrintLiveRanges(); |
| 3020 THR_Print("----------------------------------------------\n"); | 3024 THR_Print("----------------------------------------------\n"); |
| 3021 | 3025 |
| 3022 THR_Print("-- [before ssa allocator] ir [%s] -------------\n", | 3026 THR_Print("-- [before ssa allocator] ir [%s] -------------\n", |
| 3023 function.ToFullyQualifiedCString()); | 3027 function.ToFullyQualifiedCString()); |
| 3024 if (FLAG_support_il_printer) { | 3028 if (FLAG_support_il_printer) { |
| 3025 #ifndef PRODUCT | 3029 #ifndef PRODUCT |
| 3026 FlowGraphPrinter printer(flow_graph_, true); | 3030 FlowGraphPrinter printer(flow_graph_, true); |
| 3027 printer.PrintBlocks(); | 3031 printer.PrintBlocks(); |
| 3028 #endif | 3032 #endif |
| 3029 } | 3033 } |
| 3030 THR_Print("----------------------------------------------\n"); | 3034 THR_Print("----------------------------------------------\n"); |
| 3031 } | 3035 } |
| 3032 | 3036 |
| 3033 PrepareForAllocation(Location::kRegister, | 3037 PrepareForAllocation(Location::kRegister, |
| 3034 kNumberOfCpuRegisters, | 3038 kNumberOfCpuRegisters, |
| 3035 unallocated_cpu_, | 3039 unallocated_cpu_, |
| 3036 cpu_regs_, | 3040 cpu_regs_, |
| 3037 blocked_cpu_registers_); | 3041 blocked_cpu_registers_); |
| 3038 AllocateUnallocatedRanges(); | 3042 AllocateUnallocatedRanges(); |
| 3039 #if defined(TARGET_ARCH_DBC) | 3043 #if defined(TARGET_ARCH_DBC) |
| 3040 const intptr_t last_used_cpu_register = last_used_register_; | 3044 const intptr_t last_used_cpu_register = last_used_register_; |
| 3045 last_used_register_ = -1; |
| 3041 #endif | 3046 #endif |
| 3042 | 3047 |
| 3043 cpu_spill_slot_count_ = spill_slots_.length(); | 3048 cpu_spill_slot_count_ = spill_slots_.length(); |
| 3044 spill_slots_.Clear(); | 3049 spill_slots_.Clear(); |
| 3045 quad_spill_slots_.Clear(); | 3050 quad_spill_slots_.Clear(); |
| 3046 untagged_spill_slots_.Clear(); | 3051 untagged_spill_slots_.Clear(); |
| 3047 | 3052 |
| 3048 PrepareForAllocation(Location::kFpuRegister, | 3053 PrepareForAllocation(Location::kFpuRegister, |
| 3049 kNumberOfFpuRegisters, | 3054 kNumberOfFpuRegisters, |
| 3050 unallocated_xmm_, | 3055 unallocated_xmm_, |
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| 3093 FlowGraphPrinter printer(flow_graph_, true); | 3098 FlowGraphPrinter printer(flow_graph_, true); |
| 3094 printer.PrintBlocks(); | 3099 printer.PrintBlocks(); |
| 3095 #endif | 3100 #endif |
| 3096 } | 3101 } |
| 3097 THR_Print("----------------------------------------------\n"); | 3102 THR_Print("----------------------------------------------\n"); |
| 3098 } | 3103 } |
| 3099 } | 3104 } |
| 3100 | 3105 |
| 3101 | 3106 |
| 3102 } // namespace dart | 3107 } // namespace dart |
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