| OLD | NEW |
| 1 # Test rel32 jump instructions with abs32 and .reloc obstructions. | 1 # Test rel32 jump instructions with abs32 and .reloc obstructions. |
| 2 | 2 |
| 3 # Processor type | 3 # Processor type |
| 4 x64 | 4 x64 |
| 5 # .text start RVA and end RVA | 5 # .text start RVA and end RVA |
| 6 1000 | 6 1000 |
| 7 3000 | 7 3000 |
| 8 # .reloc start RVA and end RVA | 8 # .reloc start RVA and end RVA |
| 9 # Typically this won't overlap with .text. | 9 # Typically this won't overlap with .text. |
| 10 # Note: If we use 1020, then the algorithm would never encounter it, so the | 10 # Note: If we use 1020, then the algorithm would never encounter it, so the |
| (...skipping 40 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 51 004010A6: 48 8D 3D 00 00 00 lea rdi,[rip+00000000] | 51 004010A6: 48 8D 3D 00 00 00 lea rdi,[rip+00000000] |
| 52 00 | 52 00 |
| 53 004010AD: 4C 8B 05 00 00 00 mov r8,[rip+00000000] | 53 004010AD: 4C 8B 05 00 00 00 mov r8,[rip+00000000] |
| 54 00 | 54 00 |
| 55 004010B4: 4C 8B 3D 00 00 00 mov r15,[rip+00000000] | 55 004010B4: 4C 8B 3D 00 00 00 mov r15,[rip+00000000] |
| 56 00 | 56 00 |
| 57 004010BB: 4C 8D 05 00 00 00 lea r8,[rip+00000000] | 57 004010BB: 4C 8D 05 00 00 00 lea r8,[rip+00000000] |
| 58 00 | 58 00 |
| 59 004010C2: 4C 8D 3D 00 00 00 lea r15,[rip+00000000] | 59 004010C2: 4C 8D 3D 00 00 00 lea r15,[rip+00000000] |
| 60 00 | 60 00 |
| 61 004010C9: 5D pop ebp | 61 004010C9: 66 8B 05 00 00 00 mov ax,[rip+00000000] |
| 62 00 |
| 63 004010D0: 66 8B 3D 00 00 00 mov di,[rip+00000000] |
| 64 00 |
| 65 004010D7: 66 8D 05 00 00 00 lea ax,[rip+00000000] |
| 66 00 |
| 67 004010DE: 66 8D 3D 00 00 00 lea di,[rip+00000000] |
| 68 00 |
| 69 004010C9: 5D pop ebp |
| 62 004010CA: C3 ret | 70 004010CA: C3 ret |
| 63 | 71 |
| 64 Abs32: | 72 Abs32: |
| 65 1004 | 73 1004 |
| 66 1008 | 74 1008 |
| 67 105A # Straddles across two instructions. | 75 105A # Straddles across two instructions. |
| 68 105F # Same, but covers the op code (and not the target) of the second. | 76 105F # Same, but covers the op code (and not the target) of the second. |
| 69 10B3 # Straddles across two instructions. | 77 10B3 # Straddles across two instructions. |
| 70 10BA # Same, but covers the op code (and not the target) of the second. | 78 10BA # Same, but covers the op code (and not the target) of the second. |
| 71 | 79 |
| 72 Expected: | 80 Expected: |
| 73 # 1004 | 81 # 1004 |
| 74 # 1009 | 82 # 1009 |
| 75 100F | 83 100F |
| 76 1015 | 84 1015 |
| 77 101B | 85 101B |
| 78 # 1021 | 86 # 1021 |
| 79 # 1027 | 87 # 1027 |
| 80 # 102D | 88 # 102D |
| 81 1033 | 89 1033 |
| 82 1039 | 90 1039 |
| 83 103F | 91 103F |
| 84 1045 | 92 1045 |
| 85 # 1057 | 93 # 1057 |
| 86 # 105D | 94 # 105D |
| 87 1063 | 95 1063 |
| 88 1069 | 96 1069 |
| 89 106F | 97 106F |
| 90 1075 | 98 1075 |
| 91 # 107B Not yet detected. | 99 107B |
| 92 # 1081 Not yet detected. | 100 1081 |
| 93 # 1087 Not yet detected. | 101 1087 |
| 94 # 108D Not yet detected. | 102 108D |
| 95 1094 | 103 1094 |
| 96 109B | 104 109B |
| 97 10A2 | 105 10A2 |
| 98 10A9 | 106 10A9 |
| 99 # 10B0 | 107 # 10B0 |
| 100 # 10B7 | 108 # 10B7 |
| 101 10BE | 109 10BE |
| 102 10C5 | 110 10C5 |
| 111 10CC |
| 112 10D3 |
| 113 10DA |
| 114 10E1 |
| OLD | NEW |