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Issue 2069933003: Implement byte swapping instructions on MIPS32 and MIPS64. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Fix tests Created 4 years, 5 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 // A Disassembler object is used to disassemble a block of code instruction by 5 // A Disassembler object is used to disassemble a block of code instruction by
6 // instruction. The default implementation of the NameConverter object can be 6 // instruction. The default implementation of the NameConverter object can be
7 // overriden to modify register names or to do symbol lookup on addresses. 7 // overriden to modify register names or to do symbol lookup on addresses.
8 // 8 //
9 // The example below will disassemble a block of code and print it to stdout. 9 // The example below will disassemble a block of code and print it to stdout.
10 // 10 //
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1257 int sa = instr->SaFieldRaw() >> kSaShift; 1257 int sa = instr->SaFieldRaw() >> kSaShift;
1258 switch (sa) { 1258 switch (sa) {
1259 case BITSWAP: { 1259 case BITSWAP: {
1260 if (IsMipsArchVariant(kMips32r6)) { 1260 if (IsMipsArchVariant(kMips32r6)) {
1261 Format(instr, "bitswap 'rd, 'rt"); 1261 Format(instr, "bitswap 'rd, 'rt");
1262 } else { 1262 } else {
1263 Unknown(instr); 1263 Unknown(instr);
1264 } 1264 }
1265 break; 1265 break;
1266 } 1266 }
1267 case SEB: 1267 case SEB: {
1268 case SEH: 1268 if (IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) {
1269 case WSBH: 1269 Format(instr, "seb 'rd, 'rt");
1270 UNREACHABLE(); 1270 } else {
1271 Unknown(instr);
1272 }
1271 break; 1273 break;
1274 }
1275 case SEH: {
1276 if (IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) {
1277 Format(instr, "seh 'rd, 'rt");
1278 } else {
1279 Unknown(instr);
1280 }
1281 break;
1282 }
1283 case WSBH: {
1284 if (IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) {
1285 Format(instr, "wsbh 'rd, 'rt");
1286 } else {
1287 Unknown(instr);
1288 }
1289 break;
1290 }
1272 default: { 1291 default: {
1273 sa >>= kBp2Bits; 1292 sa >>= kBp2Bits;
1274 switch (sa) { 1293 switch (sa) {
1275 case ALIGN: { 1294 case ALIGN: {
1276 if (IsMipsArchVariant(kMips32r6)) { 1295 if (IsMipsArchVariant(kMips32r6)) {
1277 Format(instr, "align 'rd, 'rs, 'rt, 'bp2"); 1296 Format(instr, "align 'rd, 'rs, 'rt, 'bp2");
1278 } else { 1297 } else {
1279 Unknown(instr); 1298 Unknown(instr);
1280 } 1299 }
1281 break; 1300 break;
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1766 *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); 1785 *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
1767 } 1786 }
1768 } 1787 }
1769 1788
1770 1789
1771 #undef UNSUPPORTED 1790 #undef UNSUPPORTED
1772 1791
1773 } // namespace disasm 1792 } // namespace disasm
1774 1793
1775 #endif // V8_TARGET_ARCH_MIPS 1794 #endif // V8_TARGET_ARCH_MIPS
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