Implement byte swapping instructions on MIPS32 and MIPS64.

test/cctest/test-assembler-mips64.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 3545 matching lines @@
 
     CHECK_EQ(static_cast<int64_t>(0x000000001E58A8C3L), t.r1);
     CHECK_EQ(static_cast<int64_t>(0xFFFFFFFFD18E3F7BL), t.r2);
     CHECK_EQ(static_cast<int64_t>(0x000000001E58A8C3L), t.r3);
     CHECK_EQ(static_cast<int64_t>(0xFFFFFFFFD18E3F7BL), t.r4);
     CHECK_EQ(static_cast<int64_t>(0x08038490D18E3F7BL), t.r5);
     CHECK_EQ(static_cast<int64_t>(0xDF01E8FF1E58A8C3L), t.r6);
   }
 }
 
+TEST(SIGNEXTEND) {
+  if (kArchVariant == kMips64r6 || kArchVariant == kMips64r2) {
+    CcTest::InitializeVM();
+    Isolate* isolate = CcTest::i_isolate();
+    HandleScope scope(isolate);
+
+    typedef struct {
+      int64_t r1;
+      int64_t r2;
+      int64_t r3;
+      int64_t r4;
+    } T;
+    T t;
+
+    Assembler assm(isolate, NULL, 0);
+
+    __ ld(a4, MemOperand(a0, offsetof(T, r1)));
+    __ nop();
+    __ seh(a6, a4);
+    __ sll(a6, a6, 0);
+    __ sd(a6, MemOperand(a0, offsetof(T, r1)));
+
+    __ ld(a4, MemOperand(a0, offsetof(T, r2)));
+    __ nop();
+    __ seh(a6, a4);
+    __ sll(a6, a6, 0);
+    __ sd(a6, MemOperand(a0, offsetof(T, r2)));
+
+    __ ld(a4, MemOperand(a0, offsetof(T, r3)));
+    __ nop();
+    __ seb(a6, a4);
+    __ sll(a6, a6, 0);
+    __ sd(a6, MemOperand(a0, offsetof(T, r3)));
+
+    __ ld(a4, MemOperand(a0, offsetof(T, r4)));
+    __ nop();
+    __ seb(a6, a4);
+    __ sll(a6, a6, 0);
+    __ sd(a6, MemOperand(a0, offsetof(T, r4)));
+
+    __ jr(ra);
+    __ nop();
+
+    CodeDesc desc;
+
+    assm.GetCode(&desc);
+    Handle<Code> code = isolate->factory()->NewCode(
+        desc, Code::ComputeFlags(Code::STUB), Handle<Code>());
+
+    F3 f = FUNCTION_CAST<F3>(code->entry());
+    t.r1 = 0x15C3;
+    t.r2 = 0xFCDE;
+    t.r3 = 0xC3;
+    t.r4 = 0x5E;
+    Object* dummy = CALL_GENERATED_CODE(isolate, f, &t, 0, 0, 0, 0);
+    USE(dummy);
+
+    CHECK_EQ(static_cast<int64_t>(0x00000000000015C3), t.r1);
+    CHECK_EQ(static_cast<int64_t>(0xFFFFFFFFFFFFFCDE), t.r2);
+    CHECK_EQ(static_cast<int64_t>(0xFFFFFFFFFFFFFFC3), t.r3);
+    CHECK_EQ(static_cast<int64_t>(0x000000000000005E), t.r4);
+  }
+}
 
 TEST(class_fmt) {
   if (kArchVariant == kMips64r6) {
     // Test CLASS.fmt instruction.
     CcTest::InitializeVM();
     Isolate* isolate = CcTest::i_isolate();
     HandleScope scope(isolate);
 
     typedef struct {
       double dSignalingNan;
@@ skipping 2353 matching lines @@
       desc, Code::ComputeFlags(Code::STUB), Handle<Code>());
   F2 f = FUNCTION_CAST<F2>(code->entry());
 
   int64_t res = reinterpret_cast<int64_t>(
       CALL_GENERATED_CODE(isolate, f, 42, 42, 0, 0, 0));
   CHECK_EQ(res, 0);
 }
 
 
 #undef __