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Side by Side Diff: src/mips64/simulator-mips64.cc

Issue 2069933003: Implement byte swapping instructions on MIPS32 and MIPS64. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 4 years, 6 months ago
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1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include <limits.h> 5 #include <limits.h>
6 #include <stdarg.h> 6 #include <stdarg.h>
7 #include <stdlib.h> 7 #include <stdlib.h>
8 #include <cmath> 8 #include <cmath>
9 9
10 #if V8_TARGET_ARCH_MIPS64 10 #if V8_TARGET_ARCH_MIPS64
(...skipping 3959 matching lines...) Expand 10 before | Expand all | Expand 10 after
3970 0x10101LU >> 3970 0x10101LU >>
3971 16); 3971 16);
3972 3972
3973 output = output | (static_cast<uint32_t>(o_byte << 24)); 3973 output = output | (static_cast<uint32_t>(o_byte << 24));
3974 input = input >> 8; 3974 input = input >> 8;
3975 } 3975 }
3976 3976
3977 alu_out = static_cast<int64_t>(static_cast<int32_t>(output)); 3977 alu_out = static_cast<int64_t>(static_cast<int32_t>(output));
3978 break; 3978 break;
3979 } 3979 }
3980 case SEB: 3980 case SEB: {
3981 case SEH: 3981 int8_t input = static_cast<int8_t>(rt());
3982 case WSBH: 3982 int32_t output = 0x000000FF & input;
3983 alu_out = 0x12345678; 3983 int32_t mask = 0x00000080;
3984 UNREACHABLE(); 3984
3985 if (mask & input) output += 0xFFFFFF00;
3986
3987 alu_out = static_cast<int32_t>(output);
3985 break; 3988 break;
3989 }
3990 case SEH: {
3991 int16_t input = static_cast<int16_t>(rt());
3992 int32_t output = 0x0000FFFF & input;
3993 int32_t mask = 0x00008000;
3994
3995 if (mask & input) output += 0xFFFF0000;
3996
3997 alu_out = static_cast<int32_t>(output);
3998 break;
3999 }
4000 case WSBH: {
4001 int32_t input = static_cast<int32_t>(rt());
4002 int32_t output = 0;
4003
4004 uint32_t mask = 0xFF000000;
4005 for (int i = 0; i < 4; i++) {
4006 uint32_t tmp = mask & input;
4007 if (i % 2 == 0) {
4008 tmp = tmp >> 8;
4009 } else {
4010 tmp = tmp << 8;
4011 }
4012 output = output | tmp;
4013 mask = mask >> 8;
4014 }
4015 mask = 0x80000000;
4016
4017 if (mask & output) output += 0XFFFFFFFF00000000;
4018
4019 alu_out = static_cast<int64_t>(output);
4020 break;
4021 }
3986 default: { 4022 default: {
3987 const uint8_t bp2 = get_instr()->Bp2Value(); 4023 const uint8_t bp2 = get_instr()->Bp2Value();
3988 sa >>= kBp2Bits; 4024 sa >>= kBp2Bits;
3989 switch (sa) { 4025 switch (sa) {
3990 case ALIGN: { 4026 case ALIGN: {
3991 if (bp2 == 0) { 4027 if (bp2 == 0) {
3992 alu_out = static_cast<int32_t>(rt()); 4028 alu_out = static_cast<int32_t>(rt());
3993 } else { 4029 } else {
3994 uint64_t rt_hi = rt() << (8 * bp2); 4030 uint64_t rt_hi = rt() << (8 * bp2);
3995 uint64_t rs_lo = rs() >> (8 * (4 - bp2)); 4031 uint64_t rs_lo = rs() >> (8 * (4 - bp2));
(...skipping 38 matching lines...) Expand 10 before | Expand all | Expand 10 after
4034 output = output | ((static_cast<uint64_t>(o_byte) << 56)); 4070 output = output | ((static_cast<uint64_t>(o_byte) << 56));
4035 input = input >> 8; 4071 input = input >> 8;
4036 } 4072 }
4037 4073
4038 alu_out = static_cast<int64_t>(output); 4074 alu_out = static_cast<int64_t>(output);
4039 break; 4075 break;
4040 } 4076 }
4041 } 4077 }
4042 break; 4078 break;
4043 } 4079 }
4044 case DSBH: 4080 case DSBH: {
4045 case DSHD: 4081 int64_t input = static_cast<int64_t>(rt());
4046 alu_out = 0x12345678; 4082 int64_t output = 0;
4047 UNREACHABLE(); 4083
4084 uint64_t mask = 0xFF00000000000000;
4085 for (int i = 0; i < 8; i++) {
4086 uint64_t tmp = mask & input;
4087 if (i % 2 == 0)
4088 tmp = tmp >> 8;
4089 else
4090 tmp = tmp << 8;
4091
4092 output = output | tmp;
4093 mask = mask >> 8;
4094 }
4095
4096 alu_out = static_cast<int64_t>(output);
4048 break; 4097 break;
4098 }
4099 case DSHD: {
4100 int64_t input = static_cast<int64_t>(rt());
4101 int64_t output = 0;
4102
4103 uint64_t mask = 0xFFFF000000000000;
4104 for (int i = 0; i < 4; i++) {
4105 uint64_t tmp = mask & input;
4106 if (i == 0)
4107 tmp = tmp >> 48;
4108 else if (i == 1)
4109 tmp = tmp >> 16;
4110 else if (i == 2)
4111 tmp = tmp << 16;
4112 else
4113 tmp = tmp << 48;
4114 output = output | tmp;
4115 mask = mask >> 16;
4116 }
4117
4118 alu_out = static_cast<int64_t>(output);
4119 break;
4120 }
4049 default: { 4121 default: {
4050 const uint8_t bp3 = get_instr()->Bp3Value(); 4122 const uint8_t bp3 = get_instr()->Bp3Value();
4051 sa >>= kBp3Bits; 4123 sa >>= kBp3Bits;
4052 switch (sa) { 4124 switch (sa) {
4053 case DALIGN: { 4125 case DALIGN: {
4054 if (bp3 == 0) { 4126 if (bp3 == 0) {
4055 alu_out = static_cast<int64_t>(rt()); 4127 alu_out = static_cast<int64_t>(rt());
4056 } else { 4128 } else {
4057 uint64_t rt_hi = rt() << (8 * bp3); 4129 uint64_t rt_hi = rt() << (8 * bp3);
4058 uint64_t rs_lo = rs() >> (8 * (8 - bp3)); 4130 uint64_t rs_lo = rs() >> (8 * (8 - bp3));
(...skipping 29 matching lines...) Expand all
4088 case COP1X: 4160 case COP1X:
4089 DecodeTypeRegisterCOP1X(); 4161 DecodeTypeRegisterCOP1X();
4090 break; 4162 break;
4091 case SPECIAL: 4163 case SPECIAL:
4092 DecodeTypeRegisterSPECIAL(); 4164 DecodeTypeRegisterSPECIAL();
4093 break; 4165 break;
4094 case SPECIAL2: 4166 case SPECIAL2:
4095 DecodeTypeRegisterSPECIAL2(); 4167 DecodeTypeRegisterSPECIAL2();
4096 break; 4168 break;
4097 case SPECIAL3: 4169 case SPECIAL3:
4098 switch (instr->FunctionFieldRaw()) { 4170 DecodeTypeRegisterSPECIAL3();
4099 case BSHFL: {
4100 int32_t saVal = sa();
4101 saVal >>= kBp2Bits;
4102 switch (saVal) {
4103 case ALIGN: {
4104 DecodeTypeRegisterSPECIAL3();
4105 break;
4106 }
4107 }
4108 }
4109 case DBSHFL: {
4110 int32_t saVal = sa();
4111 saVal >>= kBp2Bits;
4112 switch (saVal) {
4113 case DALIGN: {
4114 DecodeTypeRegisterSPECIAL3();
4115 break;
4116 }
4117 }
4118 }
4119 default:
4120 DecodeTypeRegisterSPECIAL3();
4121 break;
4122 }
4123 break; 4171 break;
4124 // Unimplemented opcodes raised an error in the configuration step before, 4172 // Unimplemented opcodes raised an error in the configuration step before,
4125 // so we can use the default here to set the destination register in common 4173 // so we can use the default here to set the destination register in common
4126 // cases. 4174 // cases.
4127 default: 4175 default:
4128 UNREACHABLE(); 4176 UNREACHABLE();
4129 } 4177 }
4130 } 4178 }
4131 4179
4132 4180
(...skipping 804 matching lines...) Expand 10 before | Expand all | Expand 10 after
4937 } 4985 }
4938 4986
4939 4987
4940 #undef UNSUPPORTED 4988 #undef UNSUPPORTED
4941 } // namespace internal 4989 } // namespace internal
4942 } // namespace v8 4990 } // namespace v8
4943 4991
4944 #endif // USE_SIMULATOR 4992 #endif // USE_SIMULATOR
4945 4993
4946 #endif // V8_TARGET_ARCH_MIPS64 4994 #endif // V8_TARGET_ARCH_MIPS64
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