MIPS: Followup '[turbofan] Introduce new operators Float32SubPreserveNan and Float64SubPreserveNan'.

src/wasm/wasm-interpreter.cc

 // Copyright 2016 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/wasm/wasm-interpreter.h"
 #include "src/wasm/ast-decoder.h"
 #include "src/wasm/decoder.h"
 #include "src/wasm/wasm-external-refs.h"
 #include "src/wasm/wasm-module.h"
 
@@ skipping 42 matching lines @@
   V(I64Ne, uint64_t, !=)        \
   V(I64LtU, uint64_t, <)        \
   V(I64LeU, uint64_t, <=)       \
   V(I64GtU, uint64_t, >)        \
   V(I64GeU, uint64_t, >=)       \
   V(I64LtS, int64_t, <)         \
   V(I64LeS, int64_t, <=)        \
   V(I64GtS, int64_t, >)         \
   V(I64GeS, int64_t, >=)        \
   V(F32Add, float, +)           \
-  V(F32Sub, float, -)           \

[Marija Antic, 2016/06/17 08:09:08]

Have you run the interpreter tests on the board? Without the changes in
interpreter, RunWasmInterpreted_Float32SubMinusZero and
RunWasmInterpreted_Float32SubMinusZero were failing on the board. 

   V(F32Mul, float, *)           \
   V(F32Div, float, /)           \
   V(F32Eq, float, ==)           \
   V(F32Ne, float, !=)           \
   V(F32Lt, float, <)            \
   V(F32Le, float, <=)           \
   V(F32Gt, float, >)            \
   V(F32Ge, float, >=)           \
   V(F64Add, double, +)          \
-  V(F64Sub, double, -)          \
   V(F64Mul, double, *)          \
   V(F64Div, double, /)          \
   V(F64Eq, double, ==)          \
   V(F64Ne, double, !=)          \
   V(F64Lt, double, <)           \
   V(F64Le, double, <=)          \
   V(F64Gt, double, >)           \
   V(F64Ge, double, >=)
 
 #define FOREACH_OTHER_BINOP(V) \
   V(I32DivS, int32_t)          \
   V(I32DivU, uint32_t)         \
   V(I32RemS, int32_t)          \
   V(I32RemU, uint32_t)         \
   V(I32Shl, uint32_t)          \
   V(I32ShrU, uint32_t)         \
   V(I32ShrS, int32_t)          \
   V(I64DivS, int64_t)          \
   V(I64DivU, uint64_t)         \
   V(I64RemS, int64_t)          \
   V(I64RemU, uint64_t)         \
   V(I64Shl, uint64_t)          \
   V(I64ShrU, uint64_t)         \
   V(I64ShrS, int64_t)          \
   V(I32Ror, int32_t)           \
   V(I32Rol, int32_t)           \
   V(I64Ror, int64_t)           \
   V(I64Rol, int64_t)           \
+  V(F32Sub, float)             \
   V(F32Min, float)             \
   V(F32Max, float)             \
   V(F32CopySign, float)        \
   V(F64Min, double)            \
   V(F64Max, double)            \
+  V(F64Sub, double)            \
   V(F64CopySign, double)       \
   V(I32AsmjsDivS, int32_t)     \
   V(I32AsmjsDivU, uint32_t)    \
   V(I32AsmjsRemS, int32_t)     \
   V(I32AsmjsRemU, uint32_t)
 
 #define FOREACH_OTHER_UNOP(V)    \
   V(I32Clz, uint32_t)            \
   V(I32Ctz, uint32_t)            \
   V(I32Popcnt, uint32_t)         \
@@ skipping 187 matching lines @@
   uint64_t q = bit_cast<uint64_t>(std::numeric_limits<double>::quiet_NaN());
   if ((q & kSignalingBit) != 0) {
     // On some machines, the signaling bit set indicates it's a quiet NaN.
     return bit_cast<double>(bit_cast<uint64_t>(a) | kSignalingBit);
   } else {
     // On others, the signaling bit set indicates it's a signaling NaN.
     return bit_cast<double>(bit_cast<uint64_t>(a) & ~kSignalingBit);
   }
 }
 
+static inline float ExecuteF32Sub(float a, float b, TrapReason* trap) {
+  float result = a - b;
+  if (result - result != 0) {
+    if (std::isnan(a)) return quiet(a);
+    if (std::isnan(b)) return quiet(b);
+  }
+  return a - b;
+}
+
 static inline float ExecuteF32Min(float a, float b, TrapReason* trap) {
   if (std::isnan(a)) return quiet(a);
   if (std::isnan(b)) return quiet(b);
   return std::min(a, b);
 }
 
 static inline float ExecuteF32Max(float a, float b, TrapReason* trap) {
   if (std::isnan(a)) return quiet(a);
   if (std::isnan(b)) return quiet(b);
   return std::max(a, b);
 }
 
 static inline float ExecuteF32CopySign(float a, float b, TrapReason* trap) {
   return copysignf(a, b);
 }
 
+static inline double ExecuteF64Sub(double a, double b, TrapReason* trap) {
+  double result = a - b;
+  if (result - result != 0) {
+    if (std::isnan(a)) return quiet(a);
+    if (std::isnan(b)) return quiet(b);
+  }
+  return a - b;
+}
+
 static inline double ExecuteF64Min(double a, double b, TrapReason* trap) {
   if (std::isnan(a)) return quiet(a);
   if (std::isnan(b)) return quiet(b);
   return std::min(a, b);
 }
 
 static inline double ExecuteF64Max(double a, double b, TrapReason* trap) {
   if (std::isnan(a)) return quiet(a);
   if (std::isnan(b)) return quiet(b);
   return std::max(a, b);
@@ skipping 1459 matching lines @@
 
 ControlTransferMap WasmInterpreter::ComputeControlTransfersForTesting(
     Zone* zone, const byte* start, const byte* end) {
   ControlTransfers targets(zone, 0, start, end);
   return targets.map_;
 }
 
 }  // namespace wasm
 }  // namespace internal
 }  // namespace v8