Fix assertions wrt concurrent OSR.

src/a64/full-codegen-a64.cc

Index: src/a64/full-codegen-a64.cc
diff --git a/src/a64/full-codegen-a64.cc b/src/a64/full-codegen-a64.cc
index c95a01add5c2227560e431be9ac7378ef98b99da..b6489b21c8c26a61451def82cb52aa3e7a26c13f 100644
--- a/src/a64/full-codegen-a64.cc
+++ b/src/a64/full-codegen-a64.cc
@@ -4859,6 +4859,12 @@ void BackEdgeTable::PatchAt(Code* unoptimized_code,
   Address branch_address = pc - 3 * kInstructionSize;
   PatchingAssembler patcher(branch_address, 1);
 
+  ASSERT(Instruction::Cast(branch_address)
+             ->IsNop(Assembler::INTERRUPT_CODE_NOP) ||
+         (Instruction::Cast(branch_address)->IsCondBranchImm() &&
+          Instruction::Cast(branch_address)->ImmPCOffset() ==
+              6 * kInstructionSize));
+
   switch (target_state) {
     case INTERRUPT:
       //  <decrement profiling counter>
@@ -4868,8 +4874,6 @@ void BackEdgeTable::PatchAt(Code* unoptimized_code,
       //  ... more instructions.
       //  ok-label
       // Jump offset is 6 instructions.
-      ASSERT(Instruction::Cast(branch_address)
-                 ->IsNop(Assembler::INTERRUPT_CODE_NOP));
       patcher.b(6, pl);
       break;
     case ON_STACK_REPLACEMENT:
@@ -4878,9 +4882,6 @@ void BackEdgeTable::PatchAt(Code* unoptimized_code,
       //  .. .. .. ..       mov x0, x0 (NOP)
       //  .. .. .. ..       ldr x16, pc+<on-stack replacement address>
       //  .. .. .. ..       blr x16
-      ASSERT(Instruction::Cast(branch_address)->IsCondBranchImm());
-      ASSERT(Instruction::Cast(branch_address)->ImmPCOffset() ==
-             6 * kInstructionSize);
       patcher.nop(Assembler::INTERRUPT_CODE_NOP);
       break;
   }