Fix assertions wrt concurrent OSR.

src/a64/full-codegen-a64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 4841 matching lines @@
 
 
 void BackEdgeTable::PatchAt(Code* unoptimized_code,
                             Address pc,
                             BackEdgeState target_state,
                             Code* replacement_code) {
   // Turn the jump into a nop.
   Address branch_address = pc - 3 * kInstructionSize;
   PatchingAssembler patcher(branch_address, 1);
 
+  ASSERT(Instruction::Cast(branch_address)
+             ->IsNop(Assembler::INTERRUPT_CODE_NOP) ||
+         (Instruction::Cast(branch_address)->IsCondBranchImm() &&
+          Instruction::Cast(branch_address)->ImmPCOffset() ==
+              6 * kInstructionSize));
+
   switch (target_state) {
     case INTERRUPT:
       //  <decrement profiling counter>
       //  .. .. .. ..       b.pl ok
       //  .. .. .. ..       ldr x16, pc+<interrupt stub address>
       //  .. .. .. ..       blr x16
       //  ... more instructions.
       //  ok-label
       // Jump offset is 6 instructions.
-      ASSERT(Instruction::Cast(branch_address)
-                 ->IsNop(Assembler::INTERRUPT_CODE_NOP));
       patcher.b(6, pl);
       break;
     case ON_STACK_REPLACEMENT:
     case OSR_AFTER_STACK_CHECK:
       //  <decrement profiling counter>
       //  .. .. .. ..       mov x0, x0 (NOP)
       //  .. .. .. ..       ldr x16, pc+<on-stack replacement address>
       //  .. .. .. ..       blr x16
-      ASSERT(Instruction::Cast(branch_address)->IsCondBranchImm());
-      ASSERT(Instruction::Cast(branch_address)->ImmPCOffset() ==
-             6 * kInstructionSize);
       patcher.nop(Assembler::INTERRUPT_CODE_NOP);
       break;
   }
 
   // Replace the call address.
   Instruction* load = Instruction::Cast(pc)->preceding(2);
   Address interrupt_address_pointer =
       reinterpret_cast<Address>(load) + load->ImmPCOffset();
   ASSERT((Memory::uint64_at(interrupt_address_pointer) ==
           reinterpret_cast<uint64_t>(unoptimized_code->GetIsolate()
@@ skipping 78 matching lines @@
   return previous_;
 }
 
 
 #undef __
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_A64