Fix assertions wrt concurrent OSR.

src/a64/full-codegen-a64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
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 // modification, are permitted provided that the following conditions are
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 //
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@@ skipping 4850 matching lines @@
 
   switch (target_state) {
     case INTERRUPT:
       //  <decrement profiling counter>
       //  .. .. .. ..       b.pl ok
       //  .. .. .. ..       ldr x16, pc+<interrupt stub address>
       //  .. .. .. ..       blr x16
       //  ... more instructions.
       //  ok-label
       // Jump offset is 6 instructions.
-      ASSERT(Instruction::Cast(branch_address)
-                 ->IsNop(Assembler::INTERRUPT_CODE_NOP));
       patcher.b(6, pl);
       break;
     case ON_STACK_REPLACEMENT:
     case OSR_AFTER_STACK_CHECK:
       //  <decrement profiling counter>
       //  .. .. .. ..       mov x0, x0 (NOP)
       //  .. .. .. ..       ldr x16, pc+<on-stack replacement address>
       //  .. .. .. ..       blr x16
-      ASSERT(Instruction::Cast(branch_address)->IsCondBranchImm());
-      ASSERT(Instruction::Cast(branch_address)->ImmPCOffset() ==
-             6 * kInstructionSize);

[Yang, 2014/03/20 13:33:05]

Those assertions are bogus. We want to be able to go from any state to any other
state. For example from ON_STACK_REPLACEMENT to OSR_AFTER_STACK_CHECK.

[ulan, 2014/03/20 13:50:46]

Let's fix the asserts instead of removing them. =)
Could you move the three asserts above switch and combine them?

       patcher.nop(Assembler::INTERRUPT_CODE_NOP);
       break;
   }
 
   // Replace the call address.
   Instruction* load = Instruction::Cast(pc)->preceding(2);
   Address interrupt_address_pointer =
       reinterpret_cast<Address>(load) + load->ImmPCOffset();
   ASSERT((Memory::uint64_at(interrupt_address_pointer) ==
           reinterpret_cast<uint64_t>(unoptimized_code->GetIsolate()
@@ skipping 78 matching lines @@
   return previous_;
 }
 
 
 #undef __
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_A64