LowerCall for MIPS32

src/IceTargetLoweringMIPS32.cpp

 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost
@@ skipping 65 matching lines @@
   auto ClassNum = static_cast<RegClassMIPS32>(C);
   assert(ClassNum < RCMIPS32_NUM);
   switch (ClassNum) {
   default:
     assert(C < RC_Target);
     return regClassString(C);
     // Add handling of new register classes below.
   }
 }
 
+// Value is in bytes. Return Value adjusted to the next highest multiple of the
+// stack alignment.
+uint32_t applyStackAlignment(uint32_t Value) {
+  return Utils::applyAlignment(Value, MIPS32_STACK_ALIGNMENT_BYTES);
+}
+
 } // end of anonymous namespace
 
 TargetMIPS32::TargetMIPS32(Cfg *Func) : TargetLowering(Func) {}
 
 void TargetMIPS32::staticInit(GlobalContext *Ctx) {
   (void)Ctx;
   RegNumT::setLimit(RegMIPS32::Reg_NUM);
   SmallBitVector IntegerRegisters(RegMIPS32::Reg_NUM);
   SmallBitVector I64PairRegisters(RegMIPS32::Reg_NUM);
   SmallBitVector Float32Registers(RegMIPS32::Reg_NUM);
@@ skipping 113 matching lines @@
   // Register allocation. This requires instruction renumbering and full
   // liveness analysis.
   Func->renumberInstructions();
   if (Func->hasError())
     return;
   Func->liveness(Liveness_Intervals);
   if (Func->hasError())
     return;
   // Validate the live range computations. The expensive validation call is
   // deliberately only made when assertions are enabled.
   assert(Func->validateLiveness());

[Jim Stichnoth, 2016/06/21 13:44:00]

I recommend moving this assert (and its two comment lines above) to come *after*
the "initial MIPS32 codegen" dump.

Otherwise, it's extremely confusing to try to interpret the liveness validation
errors (running pnacl-sz with -verbose=most or -verbose=all).  This is because
the latest dump was before the instructions were renumbered for liveness
analysis, so the instruction numbers printed in the liveness validation error
messages are "wrong" with respect to the latest dump output.

BTW, if you run manually with a -verbose setting, you'll also want to run with
-threads=0 so you don't get interleaved output/execution of several different
translations.

Finally, I also limit the translation and verbose output to the single
problematic function:
  -translate-only=pass64BitArg
  -verbose-focus=pass64BitArg

[Jim Stichnoth, 2016/06/21 13:46:17]

BTW, I forgot to mention that this same change ought to be done (by me) in the
ARM and x86 targets, which suffer from the same problem.

   // The post-codegen dump is done here, after liveness analysis and associated
   // cleanup, to make the dump cleaner and more useful.
   Func->dump("After initial MIPS32 codegen");
   Func->getVMetadata()->init(VMK_All);
   regAlloc(RAK_Global);
   if (Func->hasError())
     return;
   Func->dump("After linear scan regalloc");
 
   if (getFlags().getEnablePhiEdgeSplit()) {
@@ skipping 847 matching lines @@
     case InstIcmp::Sle: {
       _slt(DestT, Src1R, Src0R);
       _br(TargetTrue, TargetFalse, DestT, CondMIPS32::Cond::NEZ);
       break;
     }
     }
   }
 }
 
 void TargetMIPS32::lowerCall(const InstCall *Instr) {
-  // TODO(rkotler): assign arguments to registers and stack. Also reserve stack.
-  if (Instr->getNumArgs()) {
-    UnimplementedLoweringError(this, Instr);
-    return;
+  NeedsStackAlignment = true;
+
+  //  Assign arguments to registers and stack. Also reserve stack.
+  TargetMIPS32::CallingConv CC;
+
+  // Pair of Arg Operand -> GPR number assignments.
+  llvm::SmallVector<std::pair<Operand *, RegNumT>, MIPS32_MAX_GPR_ARG> GPRArgs;
+  llvm::SmallVector<std::pair<Operand *, RegNumT>, MIPS32_MAX_FP_ARG> FPArgs;
+  // Pair of Arg Operand -> stack offset.
+  llvm::SmallVector<std::pair<Operand *, int32_t>, 8> StackArgs;
+  size_t ParameterAreaSizeBytes = 16;
+
+  // Classify each argument operand according to the location where the
+  // argument is passed.
+
+  for (SizeT i = 0, NumArgs = Instr->getNumArgs(); i < NumArgs; ++i) {
+    Operand *Arg = legalizeUndef(Instr->getArg(i));
+    const Type Ty = Arg->getType();
+    bool InReg = false;
+    RegNumT Reg;
+
+    InReg = CC.argInReg(Ty, i, &Reg);
+
+    if (!InReg) {
+      ParameterAreaSizeBytes =
+          applyStackAlignmentTy(ParameterAreaSizeBytes, Ty);
+      StackArgs.push_back(std::make_pair(Arg, ParameterAreaSizeBytes));
+      ParameterAreaSizeBytes += typeWidthInBytesOnStack(Ty);
+      continue;
+    }
+
+    if (Ty == IceType_i64) {
+      Operand *Lo = loOperand(Arg);
+      Operand *Hi = hiOperand(Arg);
+      GPRArgs.push_back(
+          std::make_pair(Lo, RegMIPS32::getI64PairFirstGPRNum(Reg)));
+      GPRArgs.push_back(
+          std::make_pair(Hi, RegMIPS32::getI64PairSecondGPRNum(Reg)));
+    } else if (isScalarIntegerType(Ty)) {
+      GPRArgs.push_back(std::make_pair(Arg, Reg));
+    } else {
+      FPArgs.push_back(std::make_pair(Arg, Reg));
+    }
   }
+
+  // Adjust the parameter area so that the stack is aligned. It is assumed that
+  // the stack is already aligned at the start of the calling sequence.
+  ParameterAreaSizeBytes = applyStackAlignment(ParameterAreaSizeBytes);
+
+  // Copy arguments that are passed on the stack to the appropriate stack
+  // locations.
+  Variable *SP = getPhysicalRegister(RegMIPS32::Reg_SP);
+  for (auto &StackArg : StackArgs) {
+    ConstantInteger32 *Loc =
+        llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(StackArg.second));
+    Type Ty = StackArg.first->getType();
+    OperandMIPS32Mem *Addr;
+    constexpr bool SignExt = false;
+    if (OperandMIPS32Mem::canHoldOffset(Ty, SignExt, StackArg.second)) {
+      Addr = OperandMIPS32Mem::create(Func, Ty, SP, Loc);
+    } else {
+      Variable *NewBase = Func->makeVariable(SP->getType());
+      lowerArithmetic(
+          InstArithmetic::create(Func, InstArithmetic::Add, NewBase, SP, Loc));
+      Addr = formMemoryOperand(NewBase, Ty);
+    }
+    lowerStore(InstStore::create(Func, StackArg.first, Addr));
+  }
+
   // Generate the call instruction.  Assign its result to a temporary with high
   // register allocation weight.
   Variable *Dest = Instr->getDest();
   // ReturnReg doubles as ReturnRegLo as necessary.
   Variable *ReturnReg = nullptr;
   Variable *ReturnRegHi = nullptr;
   if (Dest) {
     switch (Dest->getType()) {
     case IceType_NUM:
       llvm_unreachable("Invalid Call dest type");
@@ skipping 25 matching lines @@
       return;
     }
   }
   Operand *CallTarget = Instr->getCallTarget();
   // Allow ConstantRelocatable to be left alone as a direct call,
   // but force other constants like ConstantInteger32 to be in
   // a register and make it an indirect call.
   if (!llvm::isa<ConstantRelocatable>(CallTarget)) {
     CallTarget = legalize(CallTarget, Legal_Reg);
   }
+
+  // Copy arguments to be passed in registers to the appropriate registers.
+  CfgVector<Variable *> RegArgs;
+  for (auto &FPArg : FPArgs) {
+    RegArgs.emplace_back(legalizeToReg(FPArg.first, FPArg.second));
+  }
+  for (auto &GPRArg : GPRArgs) {
+    RegArgs.emplace_back(legalizeToReg(GPRArg.first, GPRArg.second));
+  }
+
+  // Generate a FakeUse of register arguments so that they do not get dead code
+  // eliminated as a result of the FakeKill of scratch registers after the call.
+  // These fake-uses need to be placed here to avoid argument registers from
+  // being used during the legalizeToReg() calls above.
+  for (auto *RegArg : RegArgs) {
+    Context.insert<InstFakeUse>(RegArg);
+  }
+
   Inst *NewCall = InstMIPS32Call::create(Func, ReturnReg, CallTarget);
   Context.insert(NewCall);
   if (ReturnRegHi)
     Context.insert(InstFakeDef::create(Func, ReturnRegHi));
   // Insert a register-kill pseudo instruction.
   Context.insert(InstFakeKill::create(Func, NewCall));
   // Generate a FakeUse to keep the call live if necessary.
   if (Instr->hasSideEffects() && ReturnReg) {
     Context.insert<InstFakeDef>(ReturnReg);

[Jim Stichnoth, 2016/06/21 13:44:00]

InstFakeUse

   }
   if (Dest == nullptr)
     return;
 
   // Assign the result of the call to Dest.
   if (ReturnReg) {
     if (ReturnRegHi) {
       assert(Dest->getType() == IceType_i64);
       auto *Dest64On32 = llvm::cast<Variable64On32>(Dest);
       Variable *DestLo = Dest64On32->getLo();
@@ skipping 712 matching lines @@
   Str << "\t.set\t"
       << "nomips16\n";
 }
 
 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM];
 
 } // end of namespace MIPS32
 } // end of namespace Ice