Subzero: x86-64: Allow immediates in 64-bit instructions.

src/IceTargetLoweringX86BaseImpl.h

 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 2210 matching lines @@
       _imul_imm(T, Src0, ImmConst);
       _mov(Dest, T);
     } else {
       _mov(T, Src0);
       _imul(T, Src0 == Src1 ? T : Src1);
       _mov(Dest, T);
     }
     break;
   case InstArithmetic::Shl:
     _mov(T, Src0);
-    if (!llvm::isa<ConstantInteger32>(Src1))
+    if (!llvm::isa<ConstantInteger32>(Src1) &&
+        !llvm::isa<ConstantInteger64>(Src1))
       Src1 = copyToReg8(Src1, Traits::RegisterSet::Reg_cl);
     _shl(T, Src1);
     _mov(Dest, T);
     break;
   case InstArithmetic::Lshr:
     _mov(T, Src0);
-    if (!llvm::isa<ConstantInteger32>(Src1))
+    if (!llvm::isa<ConstantInteger32>(Src1) &&
+        !llvm::isa<ConstantInteger64>(Src1))
       Src1 = copyToReg8(Src1, Traits::RegisterSet::Reg_cl);
     _shr(T, Src1);
     _mov(Dest, T);
     break;
   case InstArithmetic::Ashr:
     _mov(T, Src0);
-    if (!llvm::isa<ConstantInteger32>(Src1))
+    if (!llvm::isa<ConstantInteger32>(Src1) &&
+        !llvm::isa<ConstantInteger64>(Src1))
       Src1 = copyToReg8(Src1, Traits::RegisterSet::Reg_cl);
     _sar(T, Src1);
     _mov(Dest, T);
     break;
   case InstArithmetic::Udiv: {
     // div and idiv are the few arithmetic operators that do not allow
     // immediates as the operand.
     Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
     RegNumT Eax;
     RegNumT Edx;
@@ skipping 5076 matching lines @@
       if (isVectorType(Ty))
         return From;
       Const = llvm::cast<Constant>(From);
     }
     // There should be no constants of vector type (other than undef).
     assert(!isVectorType(Ty));
 
     // If the operand is a 64 bit constant integer we need to legalize it to a
     // register in x86-64.
     if (Traits::Is64Bit) {
-      if (llvm::isa<ConstantInteger64>(Const)) {
-        if (RegNum.hasValue()) {
-          assert(Traits::getGprForType(IceType_i64, RegNum) == RegNum);
+      if (auto *C64 = llvm::dyn_cast<ConstantInteger64>(Const)) {
+        if (!Utils::IsInt(32, C64->getValue())) {
+          if (RegNum.hasValue()) {
+            assert(Traits::getGprForType(IceType_i64, RegNum) == RegNum);
+          }
+          return copyToReg(Const, RegNum);
         }
-        return copyToReg(Const, RegNum);
       }
     }
 
     // If the operand is an 32 bit constant integer, we should check whether we
     // need to randomize it or pool it.
     if (auto *C = llvm::dyn_cast<ConstantInteger32>(Const)) {
       Operand *NewConst = randomizeOrPoolImmediate(C, RegNum);
       if (NewConst != Const) {
         return NewConst;
       }
@@ skipping 609 matching lines @@
         emitGlobal(*Var, SectionSuffix);
       }
     }
   } break;
   }
 }
 } // end of namespace X86NAMESPACE
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H