Subzero: x86-64: Allow immediates in 64-bit instructions.

src/IceInstX86BaseImpl.h

 //===- subzero/src/IceInstX86BaseImpl.h - Generic X86 instructions -*- C++ -*=//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 720 matching lines @@
     } else {
       Address SrcStackAddr = Target->stackVarToAsmOperand(SrcVar);
       (Asm->*(Emitter.GPRAddr))(Ty, VarReg, SrcStackAddr);
     }
   } else if (const auto *Mem = llvm::dyn_cast<X86OperandMem>(Src)) {
     Mem->emitSegmentOverride(Asm);
     (Asm->*(Emitter.GPRAddr))(Ty, VarReg,
                               Mem->toAsmAddress(Asm, Target, IsLea));
   } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src)) {
     (Asm->*(Emitter.GPRImm))(Ty, VarReg, AssemblerImmediate(Imm->getValue()));
+  } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger64>(Src)) {
+    assert(Traits::Is64Bit);
+    assert(Utils::IsInt(32, Imm->getValue()));
+    (Asm->*(Emitter.GPRImm))(Ty, VarReg, AssemblerImmediate(Imm->getValue()));
   } else if (const auto *Reloc = llvm::dyn_cast<ConstantRelocatable>(Src)) {
     const auto FixupKind = (Reloc->getName().hasStdString() &&
                             Reloc->getName().toString() == GlobalOffsetTable)
                                ? Traits::FK_GotPC
                                : Traits::TargetLowering::getAbsFixup();
     AssemblerFixup *Fixup = Asm->createFixup(FixupKind, Reloc);
     (Asm->*(Emitter.GPRImm))(Ty, VarReg, AssemblerImmediate(Fixup));
   } else if (const auto *Split = llvm::dyn_cast<VariableSplit>(Src)) {
     (Asm->*(Emitter.GPRAddr))(Ty, VarReg, Split->toAsmAddress(Func));
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
 template <typename TraitsType>
 void InstImpl<TraitsType>::emitIASAddrOpTyGPR(const Cfg *Func, Type Ty,
                                               const Address &Addr,
                                               const Operand *Src,
                                               const GPREmitterAddrOp &Emitter) {
   Assembler *Asm = Func->getAssembler<Assembler>();
   // Src can only be Reg or AssemblerImmediate.
   if (const auto *SrcVar = llvm::dyn_cast<Variable>(Src)) {
     assert(SrcVar->hasReg());
     GPRRegister SrcReg = Traits::getEncodedGPR(SrcVar->getRegNum());
     (Asm->*(Emitter.AddrGPR))(Ty, Addr, SrcReg);
   } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src)) {
     (Asm->*(Emitter.AddrImm))(Ty, Addr, AssemblerImmediate(Imm->getValue()));
+  } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger64>(Src)) {
+    assert(Traits::Is64Bit);
+    assert(Utils::IsInt(32, Imm->getValue()));
+    (Asm->*(Emitter.AddrImm))(Ty, Addr, AssemblerImmediate(Imm->getValue()));
   } else if (const auto *Reloc = llvm::dyn_cast<ConstantRelocatable>(Src)) {
     const auto FixupKind = (Reloc->getName().hasStdString() &&
                             Reloc->getName().toString() == GlobalOffsetTable)
                                ? Traits::FK_GotPC
                                : Traits::TargetLowering::getAbsFixup();
     AssemblerFixup *Fixup = Asm->createFixup(FixupKind, Reloc);
     (Asm->*(Emitter.AddrImm))(Ty, Addr, AssemblerImmediate(Fixup));
   } else {
     llvm_unreachable("Unexpected operand type");
   }
@@ skipping 31 matching lines @@
   assert(Var->hasReg());
   // We cheat a little and use GPRRegister even for byte operations.
   GPRRegister VarReg = Traits::getEncodedGPR(Var->getRegNum());
   // Src must be reg == ECX or an Imm8. This is asserted by the assembler.
   if (const auto *SrcVar = llvm::dyn_cast<Variable>(Src)) {
     assert(SrcVar->hasReg());
     GPRRegister SrcReg = Traits::getEncodedGPR(SrcVar->getRegNum());
     (Asm->*(Emitter.GPRGPR))(Ty, VarReg, SrcReg);
   } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src)) {
     (Asm->*(Emitter.GPRImm))(Ty, VarReg, AssemblerImmediate(Imm->getValue()));
+  } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger64>(Src)) {
+    assert(Traits::Is64Bit);
+    assert(Utils::IsInt(32, Imm->getValue()));
+    (Asm->*(Emitter.GPRImm))(Ty, VarReg, AssemblerImmediate(Imm->getValue()));
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
 template <typename TraitsType>
 void InstImpl<TraitsType>::emitIASGPRShiftDouble(
     const Cfg *Func, const Variable *Dest, const Operand *Src1Op,
     const Operand *Src2Op, const GPREmitterShiftD &Emitter) {
   Assembler *Asm = Func->getAssembler<Assembler>();
@@ skipping 1206 matching lines @@
 template <typename TraitsType>
 void InstImpl<TraitsType>::InstX86Mov::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(this->getSrcSize() == 1);
   Operand *Src = this->getSrc(0);
   Type SrcTy = Src->getType();
   Type DestTy = this->getDest()->getType();
   if (Traits::Is64Bit && DestTy == IceType_i64 &&
-      llvm::isa<ConstantInteger64>(Src)) {
+      llvm::isa<ConstantInteger64>(Src) &&
+      !Utils::IsInt(32, llvm::cast<ConstantInteger64>(Src)->getValue())) {
     Str << "\t"
            "movabs"
            "\t";
   } else {
     Str << "\t"
            "mov" << (!isScalarFloatingType(DestTy)
                          ? this->getWidthString(DestTy)
                          : Traits::TypeAttributes[DestTy].SdSsString) << "\t";
   }
   // For an integer truncation operation, src is wider than dest. In this case,
@@ skipping 869 matching lines @@
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "IACA_END";
 }
 
 } // end of namespace X86NAMESPACE
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTX86BASEIMPL_H