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Side by Side Diff: src/compiler/mips64/instruction-codes-mips64.h

Issue 2060233002: [turbofan] Prevent storing signalling NaNs into holey double arrays. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Fix spelling, rebase Created 4 years, 6 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 115 matching lines...) Expand 10 before | Expand all | Expand 10 after
126 V(Mips64Ldc1) \ 126 V(Mips64Ldc1) \
127 V(Mips64Sdc1) \ 127 V(Mips64Sdc1) \
128 V(Mips64BitcastDL) \ 128 V(Mips64BitcastDL) \
129 V(Mips64BitcastLD) \ 129 V(Mips64BitcastLD) \
130 V(Mips64Float64ExtractLowWord32) \ 130 V(Mips64Float64ExtractLowWord32) \
131 V(Mips64Float64ExtractHighWord32) \ 131 V(Mips64Float64ExtractHighWord32) \
132 V(Mips64Float64InsertLowWord32) \ 132 V(Mips64Float64InsertLowWord32) \
133 V(Mips64Float64InsertHighWord32) \ 133 V(Mips64Float64InsertHighWord32) \
134 V(Mips64Float64Max) \ 134 V(Mips64Float64Max) \
135 V(Mips64Float64Min) \ 135 V(Mips64Float64Min) \
136 V(Mips64Float64SilenceNaN) \
136 V(Mips64Float32Max) \ 137 V(Mips64Float32Max) \
137 V(Mips64Float32Min) \ 138 V(Mips64Float32Min) \
138 V(Mips64Push) \ 139 V(Mips64Push) \
139 V(Mips64StoreToStackSlot) \ 140 V(Mips64StoreToStackSlot) \
140 V(Mips64StackClaim) 141 V(Mips64StackClaim)
141 142
142 // Addressing modes represent the "shape" of inputs to an instruction. 143 // Addressing modes represent the "shape" of inputs to an instruction.
143 // Many instructions support multiple addressing modes. Addressing modes 144 // Many instructions support multiple addressing modes. Addressing modes
144 // are encoded into the InstructionCode of the instruction and tell the 145 // are encoded into the InstructionCode of the instruction and tell the
145 // code generator after register allocation which assembler method to call. 146 // code generator after register allocation which assembler method to call.
(...skipping 10 matching lines...) Expand all
156 #define TARGET_ADDRESSING_MODE_LIST(V) \ 157 #define TARGET_ADDRESSING_MODE_LIST(V) \
157 V(MRI) /* [%r0 + K] */ \ 158 V(MRI) /* [%r0 + K] */ \
158 V(MRR) /* [%r0 + %r1] */ 159 V(MRR) /* [%r0 + %r1] */
159 160
160 161
161 } // namespace compiler 162 } // namespace compiler
162 } // namespace internal 163 } // namespace internal
163 } // namespace v8 164 } // namespace v8
164 165
165 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 166 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
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