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Side by Side Diff: src/compiler/mips/instruction-codes-mips.h

Issue 2053893003: [builtins] Introduce proper base::ieee754::log. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: BUILD.gn Created 4 years, 6 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 42 matching lines...) Expand 10 before | Expand all | Expand 10 after
53 V(MipsSqrtS) \ 53 V(MipsSqrtS) \
54 V(MipsMaxS) \ 54 V(MipsMaxS) \
55 V(MipsMinS) \ 55 V(MipsMinS) \
56 V(MipsCmpD) \ 56 V(MipsCmpD) \
57 V(MipsAddD) \ 57 V(MipsAddD) \
58 V(MipsSubD) \ 58 V(MipsSubD) \
59 V(MipsMulD) \ 59 V(MipsMulD) \
60 V(MipsDivD) \ 60 V(MipsDivD) \
61 V(MipsModD) \ 61 V(MipsModD) \
62 V(MipsAbsD) \ 62 V(MipsAbsD) \
63 V(MipsLogD) \
64 V(MipsSqrtD) \ 63 V(MipsSqrtD) \
65 V(MipsMaxD) \ 64 V(MipsMaxD) \
66 V(MipsMinD) \ 65 V(MipsMinD) \
67 V(MipsAddPair) \ 66 V(MipsAddPair) \
68 V(MipsSubPair) \ 67 V(MipsSubPair) \
69 V(MipsMulPair) \ 68 V(MipsMulPair) \
70 V(MipsFloat32RoundDown) \ 69 V(MipsFloat32RoundDown) \
71 V(MipsFloat32RoundTruncate) \ 70 V(MipsFloat32RoundTruncate) \
72 V(MipsFloat32RoundUp) \ 71 V(MipsFloat32RoundUp) \
73 V(MipsFloat32RoundTiesEven) \ 72 V(MipsFloat32RoundTiesEven) \
(...skipping 58 matching lines...) Expand 10 before | Expand all | Expand 10 after
132 #define TARGET_ADDRESSING_MODE_LIST(V) \ 131 #define TARGET_ADDRESSING_MODE_LIST(V) \
133 V(MRI) /* [%r0 + K] */ \ 132 V(MRI) /* [%r0 + K] */ \
134 V(MRR) /* [%r0 + %r1] */ 133 V(MRR) /* [%r0 + %r1] */
135 134
136 135
137 } // namespace compiler 136 } // namespace compiler
138 } // namespace internal 137 } // namespace internal
139 } // namespace v8 138 } // namespace v8
140 139
141 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 140 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
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