DBC: Adds BinarySmiOp instruction

runtime/vm/constants_dbc.h

 // Copyright (c) 2016, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_CONSTANTS_DBC_H_
 #define VM_CONSTANTS_DBC_H_
 
 #include "platform/globals.h"
 #include "platform/assert.h"
 #include "platform/utils.h"
@@ skipping 65 matching lines @@
 //   | opcode |             T            |   T: signed 24-bit operand
 //   +--------+--------+--------+--------+
 //
 //
 // INSTRUCTIONS
 //
 //  - Trap
 //
 //    Unreachable instruction.
 //
+//  - Nop
+//
+//    This instuction does nothing.
+//
 //  - Compile
 //
 //    Compile current function and start executing newly produced code
 //    (used to implement LazyCompileStub);
 //
 //  - Intrinsic id
 //
 //    Execute intrinsic with the given id. If intrinsic returns true then
 //    return from the current function to the caller passing value produced
 //    by the intrinsic as a result;
@@ skipping 57 matching lines @@
 //    Invoke native function SP[-1] with argc_tag SP[0].
 //
 //  - AddTOS; SubTOS; MulTOS; BitOrTOS; BitAndTOS; EqualTOS; LessThanTOS;
 //    GreaterThanTOS;
 //
 //    Smi fast-path for a corresponding method. Checks if SP[0] and SP[-1] are
 //    both smis and result of SP[0] <op> SP[-1] is a smi - if this is true
 //    then pops operands and pushes result on the stack and skips the next
 //    instruction (which implements a slow path fallback).
 //
+//  - Add, Sub, Mul, Div, Mod, Shl, Shr rA, rB, rC
+//
+//    Arithmetic operations on Smis. FP[rA] <- FP[rB] op FP[rC].
+//    If these instructions can trigger a deoptimization, the following
+//    instruction should be Deopt. If no deoptimization should be triggered,
+//    the immediately following instruction is skipped. These instructions
+//    expect their operands to be Smis, but don't check that they are.
+//
+//  - BitOr, BitAnd, BitXor rA, rB, rC
+//
+//    FP[rA] <- FP[rB] op FP[rC]. These instructions expect their operands to be
+//    Smis, but don't check that they are.
+//
 //  - StoreStaticTOS D
 //
 //    Stores TOS into the static field PP[D].
 //
 //  - PushStatic
 //
 //    Pushes value of the static field PP[D] on to the stack.
 //
 //  - InitStaticTOS
 //
@@ skipping 209 matching lines @@
 //     reg register (unsigned FP relative local)
 //     xeg x-register (signed FP relative local)
 //     tgt jump target relative to the PC of the current instruction
 //
 // TODO(vegorov) jump targets should be encoded relative to PC of the next
 //               instruction because PC is incremeted immediately after fetch
 //               and before decoding.
 //
 #define BYTECODES_LIST(V)                              \
   V(Trap,                            0, ___, ___, ___) \
+  V(Nop,                             0, ___, ___, ___) \
   V(Compile,                         0, ___, ___, ___) \
   V(HotCheck,                      A_D, num, num, ___) \
   V(Intrinsic,                       A, num, ___, ___) \
   V(Drop1,                           0, ___, ___, ___) \
   V(DropR,                           A, num, ___, ___) \
   V(Drop,                            A, num, ___, ___) \
   V(Jump,                            T, tgt, ___, ___) \
   V(Return,                          A, reg, ___, ___) \
   V(ReturnTOS,                       0, ___, ___, ___) \
   V(Move,                          A_X, reg, xeg, ___) \
@@ skipping 13 matching lines @@
   V(NativeCall,                      0, ___, ___, ___) \
   V(NativeBootstrapCall,             0, ___, ___, ___) \
   V(AddTOS,                          0, ___, ___, ___) \
   V(SubTOS,                          0, ___, ___, ___) \
   V(MulTOS,                          0, ___, ___, ___) \
   V(BitOrTOS,                        0, ___, ___, ___) \
   V(BitAndTOS,                       0, ___, ___, ___) \
   V(EqualTOS,                        0, ___, ___, ___) \
   V(LessThanTOS,                     0, ___, ___, ___) \
   V(GreaterThanTOS,                  0, ___, ___, ___) \
+  V(Add,                         A_B_C, reg, reg, reg) \
+  V(Sub,                         A_B_C, reg, reg, reg) \
+  V(Mul,                         A_B_C, reg, reg, reg) \
+  V(Div,                         A_B_C, reg, reg, reg) \
+  V(Mod,                         A_B_C, reg, reg, reg) \
+  V(BitOr,                       A_B_C, reg, reg, reg) \
+  V(BitAnd,                      A_B_C, reg, reg, reg) \
+  V(BitXor,                      A_B_C, reg, reg, reg) \
+  V(Shl,                         A_B_C, reg, reg, reg) \
+  V(Shr,                         A_B_C, reg, reg, reg) \
   V(StoreStaticTOS,                  D, lit, ___, ___) \
   V(PushStatic,                      D, lit, ___, ___) \
   V(InitStaticTOS,                   0, ___, ___, ___) \
   V(IfNeStrictTOS,                   0, ___, ___, ___) \
   V(IfEqStrictTOS,                   0, ___, ___, ___) \
   V(IfNeStrictNumTOS,                0, ___, ___, ___) \
   V(IfEqStrictNumTOS,                0, ___, ___, ___) \
   V(IfNeStrict,                    A_D, reg, reg, ___) \
   V(IfEqStrict,                    A_D, reg, reg, ___) \
   V(IfNeStrictNum,                 A_D, reg, reg, ___) \
@@ skipping 138 matching lines @@
   kNumberOfDummyFpuRegisters,
 };
 const FpuRegister FpuTMP = kFakeFpuRegister;
 const intptr_t kNumberOfFpuRegisters = 1;
 
 enum Condition { EQ, NE };
 
 }  // namespace dart
 
 #endif  // VM_CONSTANTS_DBC_H_