Calling convention for MIPS32

src/IceTargetLoweringMIPS32.h

 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 441 matching lines @@
 
   // Ensure that a 64-bit Variable has been split into 2 32-bit
   // Variables, creating them if necessary.  This is needed for all
   // I64 operations.
   void split64(Variable *Var);
   Operand *loOperand(Operand *Operand);
   Operand *hiOperand(Operand *Operand);
 
   Operand *legalizeUndef(Operand *From, RegNumT RegNum = RegNumT());
 
+  /// Helper class that understands the Calling Convention and register
+  /// assignments as per MIPS O32 abi.
+  class CallingConv {
+    CallingConv(const CallingConv &) = delete;
+    CallingConv &operator=(const CallingConv &) = delete;
+
+  public:
+    CallingConv();
+    ~CallingConv() = default;
+
+    /// argInReg returns true if there is a Register available for the requested
+    /// type, and false otherwise. If it returns true, Reg is set to the
+    /// appropriate register number. Note that, when Ty == IceType_i64, Reg will
+    /// be an I64 register pair.
+    bool argInReg(Type Ty, uint32_t ArgNo, RegNumT *Reg);
+
+  private:
+    // argInGPR is used to find if any GPR register is available for argument of
+    // type Ty
+    bool argInGPR(Type Ty, RegNumT *Reg);
+    /// argInVFP is to floating-point/vector types what argInGPR is for integer
+    /// types.
+    bool argInVFP(Type Ty, RegNumT *Reg);
+    inline void discardNextGPRAndItsAliases(CfgVector<RegNumT> *Regs);
+    void discardUnavailableGPRsAndTheirAliases(CfgVector<RegNumT> *Regs);
+    SmallBitVector GPRegsUsed;
+    CfgVector<RegNumT> GPRArgs;
+    CfgVector<RegNumT> I64Args;
+
+    void discardUnavailableVFPRegsAndTheirAliases(CfgVector<RegNumT> *Regs);
+    SmallBitVector VFPRegsUsed;
+    CfgVector<RegNumT> FP32Args;
+    CfgVector<RegNumT> FP64Args;
+    // UseFPRegs is a flag indicating if FP registers can be used
+    bool UseFPRegs = false;
+  };
+
 protected:
   explicit TargetMIPS32(Cfg *Func);
 
   void postLower() override;
 
   void lowerAlloca(const InstAlloca *Instr) override;
   void lowerArithmetic(const InstArithmetic *Instr) override;
   void lowerInt64Arithmetic(const InstArithmetic *Instr, Variable *Dest,
                             Operand *Src0, Operand *Src1);
   void lowerAssign(const InstAssign *Instr) override;
@@ skipping 145 matching lines @@
   explicit TargetHeaderMIPS32(GlobalContext *Ctx);
 
 private:
   ~TargetHeaderMIPS32() = default;
 };
 
 } // end of namespace MIPS32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H