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Unified Diff: src/IceTargetLoweringX8664.cpp

Issue 2052683003: Subzero: Improve effectiveness of local register availability peephole. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fix comments. Implement for x86-32. Created 4 years, 6 months ago
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Index: src/IceTargetLoweringX8664.cpp
diff --git a/src/IceTargetLoweringX8664.cpp b/src/IceTargetLoweringX8664.cpp
index 73ad386b536b39e6bff74661b43ba138d5021ac2..37b7b36a5441d512a7acc5e095650d4e8bd1d884 100644
--- a/src/IceTargetLoweringX8664.cpp
+++ b/src/IceTargetLoweringX8664.cpp
@@ -485,25 +485,29 @@ Traits::X86OperandMem *TargetX8664::_sandbox_mem_reference(X86OperandMem *Mem) {
void TargetX8664::_sub_sp(Operand *Adjustment) {
Variable *rsp =
getPhysicalRegister(Traits::RegisterSet::Reg_rsp, Traits::WordType);
- if (!NeedSandboxing) {
+
+ if (NeedSandboxing) {
+ Variable *esp =
+ getPhysicalRegister(Traits::RegisterSet::Reg_esp, IceType_i32);
+ Variable *r15 =
+ getPhysicalRegister(Traits::RegisterSet::Reg_r15, IceType_i64);
+
+ // .bundle_start
+ // sub Adjustment, %esp
+ // add %r15, %rsp
+ // .bundle_end
+ AutoBundle _(this);
+ _redefined(Context.insert<InstFakeDef>(esp, rsp));
+ _sub(esp, Adjustment);
+ _redefined(Context.insert<InstFakeDef>(rsp, esp));
+ _add(rsp, r15);
+ } else {
_sub(rsp, Adjustment);
- return;
}
- Variable *esp =
- getPhysicalRegister(Traits::RegisterSet::Reg_esp, IceType_i32);
- Variable *r15 =
- getPhysicalRegister(Traits::RegisterSet::Reg_r15, IceType_i64);
-
- // .bundle_start
- // sub Adjustment, %esp
- // add %r15, %rsp
- // .bundle_end
- AutoBundle _(this);
- _redefined(Context.insert<InstFakeDef>(esp, rsp));
- _sub(esp, Adjustment);
- _redefined(Context.insert<InstFakeDef>(rsp, esp));
- _add(rsp, r15);
+ // Add a fake use of the stack pointer, to prevent the stack pointer adustment
+ // from being dead-code eliminated in a function that doesn't return.
+ Context.insert<InstFakeUse>(rsp);
}
void TargetX8664::initRebasePtr() {
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