Subzero: Improve effectiveness of local register availability peephole.

src/IceTargetLoweringX86BaseImpl.h

 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 1488 matching lines @@
         Func, IceType_void, esp, Ctx->getConstantInt(IceType_i32, OutArgsSize));
     _lea(T, CalculateOperand);
     _mov(Dest, T);
   } else {
     _mov(Dest, esp);
   }
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::lowerArguments() {
+  const bool OptM1 = Func->getOptLevel() == Opt_m1;
   VarList &Args = Func->getArgs();
   unsigned NumXmmArgs = 0;
   bool XmmSlotsRemain = true;
   unsigned NumGprArgs = 0;
   bool GprSlotsRemain = true;
 
   Context.init(Func->getEntryNode());
   Context.setInsertPoint(Context.getCur());
 
   for (SizeT i = 0, End = Args.size();
@@ skipping 35 matching lines @@
     // Replace Arg in the argument list with the home register. Then generate
     // an instruction in the prolog to copy the home register to the assigned
     // location of Arg.
     if (BuildDefs::dump())
       RegisterArg->setName(Func, "home_reg:" + Arg->getName());
     RegisterArg->setRegNum(RegNum);
     RegisterArg->setIsArg();
     Arg->setIsArg(false);
 
     Args[i] = RegisterArg;
-    Context.insert<InstAssign>(Arg, RegisterArg);
+    // When not Om1, do the assignment through a temporary, instead of directly
+    // from the pre-colored variable, so that a subsequent availabilityGet()
+    // call has a chance to work.  (In Om1, don't bother creating extra
+    // instructions with extra variables to register-allocate.)
+    if (OptM1) {
+      Context.insert<InstAssign>(Arg, RegisterArg);
+    } else {
+      Variable *Tmp = makeReg(RegisterArg->getType());
+      Context.insert<InstAssign>(Tmp, RegisterArg);
+      Context.insert<InstAssign>(Arg, Tmp);
+    }
   }
+  if (!OptM1)
+    Context.availabilityUpdate();
 }
 
 /// Strength-reduce scalar integer multiplication by a constant (for i32 or
 /// narrower) for certain constants. The lea instruction can be used to multiply
 /// by 3, 5, or 9, and the lsh instruction can be used to multiply by powers of
 /// 2. These can be combined such that e.g. multiplying by 100 can be done as 2
 /// lea-based multiplies by 5, combined with left-shifting by 2.
 template <typename TraitsType>
 bool TargetX86Base<TraitsType>::optimizeScalarMul(Variable *Dest, Operand *Src0,
                                                   int32_t Src1) {
@@ skipping 1005 matching lines @@
       ParameterAreaSizeBytes =
           std::max(static_cast<size_t>(ParameterAreaSizeBytes),
                    typeWidthInBytesOnStack(DestTy));
     }
   }
   // Adjust the parameter area so that the stack is aligned. It is assumed that
   // the stack is already aligned at the start of the calling sequence.
   ParameterAreaSizeBytes = Traits::applyStackAlignment(ParameterAreaSizeBytes);
   assert(ParameterAreaSizeBytes <= maxOutArgsSizeBytes());
   // Copy arguments that are passed on the stack to the appropriate stack
-  // locations.
+  // locations.  We make sure legalize() is called on each argument at this
+  // point, to allow availabilityGet() to work.
   for (SizeT i = 0, NumStackArgs = StackArgs.size(); i < NumStackArgs; ++i) {
-    lowerStore(InstStore::create(Func, StackArgs[i], StackArgLocations[i]));
+    lowerStore(
+        InstStore::create(Func, legalize(StackArgs[i]), StackArgLocations[i]));
   }
   // Copy arguments to be passed in registers to the appropriate registers.
   for (SizeT i = 0, NumXmmArgs = XmmArgs.size(); i < NumXmmArgs; ++i) {
-    Variable *Reg =
-        legalizeToReg(XmmArgs[i], Traits::getRegisterForXmmArgNum(i));
-    // Generate a FakeUse of register arguments so that they do not get dead
-    // code eliminated as a result of the FakeKill of scratch registers after
-    // the call.
-    Context.insert<InstFakeUse>(Reg);
+    XmmArgs[i] =
+        legalizeToReg(legalize(XmmArgs[i]), Traits::getRegisterForXmmArgNum(i));
   }
   // Materialize moves for arguments passed in GPRs.
   for (SizeT i = 0, NumGprArgs = GprArgs.size(); i < NumGprArgs; ++i) {
     const Type SignatureTy = GprArgs[i].first;
-    Operand *Arg = GprArgs[i].second;
-    Variable *Reg =
+    Operand *Arg = legalize(GprArgs[i].second);
+    GprArgs[i].second =
         legalizeToReg(Arg, Traits::getRegisterForGprArgNum(Arg->getType(), i));
     assert(SignatureTy == IceType_i64 || SignatureTy == IceType_i32);
     assert(SignatureTy == Arg->getType());
     (void)SignatureTy;
-    Context.insert<InstFakeUse>(Reg);
+  }
+  // Generate a FakeUse of register arguments so that they do not get dead code
+  // eliminated as a result of the FakeKill of scratch registers after the call.
+  // These need to be right before the call instruction.
+  for (auto *Arg : XmmArgs) {
+    Context.insert<InstFakeUse>(llvm::cast<Variable>(Arg));
+  }
+  for (auto &ArgPair : GprArgs) {
+    Context.insert<InstFakeUse>(llvm::cast<Variable>(ArgPair.second));
   }
   // Generate the call instruction. Assign its result to a temporary with high
   // register allocation weight.
   // ReturnReg doubles as ReturnRegLo as necessary.
   Variable *ReturnReg = nullptr;
   Variable *ReturnRegHi = nullptr;
   if (Dest) {
     switch (DestTy) {
     case IceType_NUM:
     case IceType_void:
@@ skipping 5323 matching lines @@
         emitGlobal(*Var, SectionSuffix);
       }
     }
   } break;
   }
 }
 } // end of namespace X86NAMESPACE
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H