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Issue 2051713002: [Subzero][MIPS32] Adds prolog instructions for MIPS32 (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Changes related to calling convention Created 4 years, 6 months ago
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1 //===- subzero/src/IceInstMIPS32.def - X-Macros for MIPS insts --*- C++ -*-===// 1 //===- subzero/src/IceInstMIPS32.def - X-Macros for MIPS insts --*- C++ -*-===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file defines properties of MIPS32 instructions in the form of x-macros. 10 // This file defines properties of MIPS32 instructions in the form of x-macros.
(...skipping 83 matching lines...) Expand 10 before | Expand all | Expand 10 after
94 X(Reg_K0, 26, "k0", 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 94 X(Reg_K0, 26, "k0", 0, 0, 0, 0, 0, 0, 0, 0, 0, \
95 ALIASES1(Reg_K0)) \ 95 ALIASES1(Reg_K0)) \
96 X(Reg_K1, 27, "k1", 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 96 X(Reg_K1, 27, "k1", 0, 0, 0, 0, 0, 0, 0, 0, 0, \
97 ALIASES1(Reg_K1)) \ 97 ALIASES1(Reg_K1)) \
98 X(Reg_GP, 28, "gp", 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 98 X(Reg_GP, 28, "gp", 0, 0, 0, 0, 0, 0, 0, 0, 0, \
99 ALIASES1(Reg_GP)) \ 99 ALIASES1(Reg_GP)) \
100 X(Reg_SP, 29, "sp", 0, 0, 1, 0, 0, 0, 0, 0, 0, \ 100 X(Reg_SP, 29, "sp", 0, 0, 1, 0, 0, 0, 0, 0, 0, \
101 ALIASES1(Reg_SP)) \ 101 ALIASES1(Reg_SP)) \
102 X(Reg_FP, 30, "fp", 0, 0, 0, 1, 0, 0, 0, 0, 0, \ 102 X(Reg_FP, 30, "fp", 0, 0, 0, 1, 0, 0, 0, 0, 0, \
103 ALIASES1(Reg_FP)) \ 103 ALIASES1(Reg_FP)) \
104 X(Reg_RA, 31, "ra", 0, 1, 0, 0, 0, 0, 0, 0, 0, \ 104 X(Reg_RA, 31, "ra", 0, 0, 0, 0, 0, 0, 0, 0, 0, \
105 ALIASES1(Reg_RA)) \ 105 ALIASES1(Reg_RA)) \
106 X(Reg_LO, 0, "lo", 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 106 X(Reg_LO, 0, "lo", 0, 0, 0, 0, 0, 0, 0, 0, 0, \
107 ALIASES2(Reg_LO, Reg_LOHI)) \ 107 ALIASES2(Reg_LO, Reg_LOHI)) \
108 X(Reg_HI, 0, "hi", 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 108 X(Reg_HI, 0, "hi", 0, 0, 0, 0, 0, 0, 0, 0, 0, \
109 ALIASES2(Reg_HI, Reg_LOHI)) 109 ALIASES2(Reg_HI, Reg_LOHI))
110 110
111 #define REGMIPS32_FPR_TABLE \ 111 #define REGMIPS32_FPR_TABLE \
112 /* val, encode, name, scratch, preserved, stackptr, frameptr, \ 112 /* val, encode, name, scratch, preserved, stackptr, frameptr, \
113 isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \ 113 isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \
114 X(Reg_F0, 0, "f0", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F0)) \ 114 X(Reg_F0, 0, "f0", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F0)) \
(...skipping 138 matching lines...) Expand 10 before | Expand all | Expand 10 after
253 X(NEZ, EQZ, "nez") /* signed not equal to zero */ \ 253 X(NEZ, EQZ, "nez") /* signed not equal to zero */ \
254 X(GEZ, LTZ, "gez") /* signed greater than or equal to zero */ \ 254 X(GEZ, LTZ, "gez") /* signed greater than or equal to zero */ \
255 X(LTZ, GEZ, "ltz") /* signed less than to zero */ \ 255 X(LTZ, GEZ, "ltz") /* signed less than to zero */ \
256 X(GTZ, LEZ, "gtz") /* signed greater than to zero */ \ 256 X(GTZ, LEZ, "gtz") /* signed greater than to zero */ \
257 X(LEZ, GTZ, "lez") /* signed less than or equal to zero */ \ 257 X(LEZ, GTZ, "lez") /* signed less than or equal to zero */ \
258 X(AL, kNone, "") /* always (unconditional) */ \ 258 X(AL, kNone, "") /* always (unconditional) */ \
259 X(kNone, kNone, "??") /* special condition / none */ 259 X(kNone, kNone, "??") /* special condition / none */
260 //#define X(tag, opp, emit) 260 //#define X(tag, opp, emit)
261 261
262 #endif // SUBZERO_SRC_ICEINSTMIPS32_DEF 262 #endif // SUBZERO_SRC_ICEINSTMIPS32_DEF
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