Subzero, MIPS32: Floating point comparison

src/IceTargetLoweringMIPS32.cpp

Index: src/IceTargetLoweringMIPS32.cpp
diff --git a/src/IceTargetLoweringMIPS32.cpp b/src/IceTargetLoweringMIPS32.cpp
index 7bdf723d3796b4da898c12e1f0a54380a7fbff89..b601178f028a60cddf58eab54d31329609a1c479 100644
--- a/src/IceTargetLoweringMIPS32.cpp
+++ b/src/IceTargetLoweringMIPS32.cpp
@@ -2052,7 +2052,186 @@ void TargetMIPS32::lowerExtractElement(const InstExtractElement *Instr) {
 }
 
 void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) {
-  UnimplementedLoweringError(this, Instr);
+

[Jim Stichnoth, 2016/09/12 14:14:41]

delete this blank line?

[obucinac, 2016/09/12 19:16:16]

Done.

+  Variable *Dest = Instr->getDest();
+  if (isVectorType(Dest->getType())) {
+    UnimplementedLoweringError(this, Instr);
+    return;
+  }
+
+  auto *Src0 = Instr->getSrc(0);
+  auto *Src1 = Instr->getSrc(1);
+  auto *Zero = getZero();
+
+  InstFcmp::FCond Cond = Instr->getCondition();
+  auto *DestR = legalizeToReg(Dest);
+  auto *Src0R = legalizeToReg(Src0);
+  auto *Src1R = legalizeToReg(Src1);
+  const Type Src0Ty = Src0->getType();
+
+  Operand *FCC0 = OperandMIPS32FCC::create(getContext().getNode()->getCfg(),

[Jim Stichnoth, 2016/09/12 14:14:41]

You can just use TargetLowering::getFunc() here.

[obucinac, 2016/09/12 19:16:16]

Done.

+                                           IceType_i32, OperandMIPS32FCC::FCC0);
+
+  switch (Cond) {
+  default: {
+    UnimplementedLoweringError(this, Instr);
+    return;
+  }
+  case InstFcmp::False: {
+    Context.insert<InstFakeUse>(Src0R);
+    Context.insert<InstFakeUse>(Src1R);
+    _addiu(DestR, Zero, 0);
+    _mov(Dest, DestR);
+    break;
+  }
+  case InstFcmp::Oeq: {

[Jim Stichnoth, 2016/09/12 14:14:41]

Does the MIPS instruction set really provide a 1:1 mapping for the 14
ordered/unordered LLVM fcmp conditions?  If so, that is amazing.  See for
example the complex lowering that ARM and x86 have to do for the NaN situations.

In any case, I'll have full confidence once the test_fcmp cross test is running.

[obucinac, 2016/09/12 19:16:16]

This is related link:

https://imagination-technologies-cloudfront-assets.s3.amazonaws.com/documenta...

Page number 108.

MIPS instruction C.cond.fmt have in total 48 variants, 16 variants per type,
where we are using only some variants for 32bit and 64bit floats. If I
understand instruction reference correctly, I believe that there is a 1:1 match.
Some of them are achieved by negating comparison result, which is basically done
by movt and movf conditional moves.

To make this change, I compiled test file with llc for mips32, disassembled it
and followed the output.

I will try to merge this patch with crosstest patch, to see results, and report
them back here.

+    if (Src0Ty == IceType_f32) {
+      _c_eq_s(Src0R, Src1R);
+    } else {
+      _c_eq_d(Src0R, Src1R);
+    }
+    _movf(DestR, Zero, FCC0);
+    _mov(Dest, DestR);
+    break;
+  }
+  case InstFcmp::Ogt: {
+    if (Src0Ty == IceType_f32) {
+      _c_ule_s(Src0R, Src1R);
+    } else {
+      _c_ule_d(Src0R, Src1R);
+    }
+    _movt(DestR, Zero, FCC0);
+    _mov(Dest, DestR);
+    break;
+  }
+  case InstFcmp::Oge: {
+    if (Src0Ty == IceType_f32) {
+      _c_ult_s(Src0R, Src1R);
+    } else {
+      _c_ult_d(Src0R, Src1R);
+    }
+    _movt(DestR, Zero, FCC0);
+    _mov(Dest, DestR);
+    break;
+  }
+  case InstFcmp::Olt: {
+    if (Src0Ty == IceType_f32) {
+      _c_olt_s(Src0R, Src1R);
+    } else {
+      _c_olt_d(Src0R, Src1R);
+    }
+    _movf(DestR, Zero, FCC0);
+    _mov(Dest, DestR);
+    break;
+  }
+  case InstFcmp::Ole: {
+    if (Src0Ty == IceType_f32) {
+      _c_ole_s(Src0R, Src1R);
+    } else {
+      _c_ole_d(Src0R, Src1R);
+    }
+    _movf(DestR, Zero, FCC0);
+    _mov(Dest, DestR);
+    break;
+  }
+  case InstFcmp::One: {
+    if (Src0Ty == IceType_f32) {
+      _c_ueq_s(Src0R, Src1R);
+    } else {
+      _c_ueq_d(Src0R, Src1R);
+    }
+    _movt(DestR, Zero, FCC0);
+    _mov(Dest, DestR);
+    break;
+  }
+  case InstFcmp::Ord: {
+    if (Src0Ty == IceType_f32) {
+      _c_un_s(Src0R, Src1R);
+    } else {
+      _c_un_d(Src0R, Src1R);
+    }
+    _movt(DestR, Zero, FCC0);
+    _mov(Dest, DestR);
+    break;
+  }
+  case InstFcmp::Ueq: {
+    if (Src0Ty == IceType_f32) {
+      _c_ueq_s(Src0R, Src1R);
+    } else {
+      _c_ueq_d(Src0R, Src1R);
+    }
+    _movf(DestR, Zero, FCC0);
+    _mov(Dest, DestR);
+    break;
+  }
+  case InstFcmp::Ugt: {
+    if (Src0Ty == IceType_f32) {
+      _c_ole_s(Src0R, Src1R);
+    } else {
+      _c_ole_d(Src0R, Src1R);
+    }
+    _movt(DestR, Zero, FCC0);
+    _mov(Dest, DestR);
+    break;
+  }
+  case InstFcmp::Uge: {
+    if (Src0Ty == IceType_f32) {
+      _c_olt_s(Src0R, Src1R);
+    } else {
+      _c_olt_d(Src0R, Src1R);
+    }
+    _movt(DestR, Zero, FCC0);
+    _mov(Dest, DestR);
+    break;
+  }
+  case InstFcmp::Ult: {
+    if (Src0Ty == IceType_f32) {
+      _c_ult_s(Src0R, Src1R);
+    } else {
+      _c_ult_d(Src0R, Src1R);
+    }
+    _movf(DestR, Zero, FCC0);
+    _mov(Dest, DestR);
+    break;
+  }
+  case InstFcmp::Ule: {
+    if (Src0Ty == IceType_f32) {
+      _c_ule_s(Src0R, Src1R);
+    } else {
+      _c_ule_d(Src0R, Src1R);
+    }
+    _movf(DestR, Zero, FCC0);
+    _mov(Dest, DestR);
+    break;
+  }
+  case InstFcmp::Une: {
+    if (Src0Ty == IceType_f32) {
+      _c_eq_s(Src0R, Src1R);
+    } else {
+      _c_eq_d(Src0R, Src1R);
+    }
+    _movt(DestR, Zero, FCC0);
+    _mov(Dest, DestR);
+    break;
+  }
+  case InstFcmp::Uno: {
+    if (Src0Ty == IceType_f32) {
+      _c_un_s(Src0R, Src1R);
+    } else {
+      _c_un_d(Src0R, Src1R);
+    }
+    _movf(DestR, Zero, FCC0);
+    _mov(Dest, DestR);
+    break;
+  }
+  case InstFcmp::True: {
+    Context.insert<InstFakeUse>(Src0R);
+    Context.insert<InstFakeUse>(Src1R);
+    _addiu(DestR, Zero, 1);
+    _mov(Dest, DestR);
+    break;
+  }
+  }
 }
 
 void TargetMIPS32::lower64Icmp(const InstIcmp *Instr) {