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1 // | 1 // |
2 // The Subzero Code Generator | 2 // The Subzero Code Generator |
3 // | 3 // |
4 // This file is distributed under the University of Illinois Open Source | 4 // This file is distributed under the University of Illinois Open Source |
5 // License. See LICENSE.TXT for details. | 5 // License. See LICENSE.TXT for details. |
6 // | 6 // |
7 //===----------------------------------------------------------------------===// | 7 //===----------------------------------------------------------------------===// |
8 /// | 8 /// |
9 /// \file | 9 /// \file |
10 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost | 10 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost |
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2429 break; | 2429 break; |
2430 } | 2430 } |
2431 } | 2431 } |
2432 } | 2432 } |
2433 | 2433 |
2434 void TargetMIPS32::lowerExtractElement(const InstExtractElement *Instr) { | 2434 void TargetMIPS32::lowerExtractElement(const InstExtractElement *Instr) { |
2435 UnimplementedLoweringError(this, Instr); | 2435 UnimplementedLoweringError(this, Instr); |
2436 } | 2436 } |
2437 | 2437 |
2438 void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) { | 2438 void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) { |
2439 UnimplementedLoweringError(this, Instr); | 2439 Variable *Dest = Instr->getDest(); |
| 2440 if (isVectorType(Dest->getType())) { |
| 2441 UnimplementedLoweringError(this, Instr); |
| 2442 return; |
| 2443 } |
| 2444 |
| 2445 auto *Src0 = Instr->getSrc(0); |
| 2446 auto *Src1 = Instr->getSrc(1); |
| 2447 auto *Zero = getZero(); |
| 2448 |
| 2449 InstFcmp::FCond Cond = Instr->getCondition(); |
| 2450 auto *DestR = legalizeToReg(Dest); |
| 2451 auto *Src0R = legalizeToReg(Src0); |
| 2452 auto *Src1R = legalizeToReg(Src1); |
| 2453 const Type Src0Ty = Src0->getType(); |
| 2454 |
| 2455 Operand *FCC0 = OperandMIPS32FCC::create(getFunc(), OperandMIPS32FCC::FCC0); |
| 2456 |
| 2457 switch (Cond) { |
| 2458 default: { |
| 2459 UnimplementedLoweringError(this, Instr); |
| 2460 return; |
| 2461 } |
| 2462 case InstFcmp::False: { |
| 2463 Context.insert<InstFakeUse>(Src0R); |
| 2464 Context.insert<InstFakeUse>(Src1R); |
| 2465 _addiu(DestR, Zero, 0); |
| 2466 _mov(Dest, DestR); |
| 2467 break; |
| 2468 } |
| 2469 case InstFcmp::Oeq: { |
| 2470 if (Src0Ty == IceType_f32) { |
| 2471 _c_eq_s(Src0R, Src1R); |
| 2472 } else { |
| 2473 _c_eq_d(Src0R, Src1R); |
| 2474 } |
| 2475 _movf(DestR, Zero, FCC0); |
| 2476 _mov(Dest, DestR); |
| 2477 break; |
| 2478 } |
| 2479 case InstFcmp::Ogt: { |
| 2480 if (Src0Ty == IceType_f32) { |
| 2481 _c_ule_s(Src0R, Src1R); |
| 2482 } else { |
| 2483 _c_ule_d(Src0R, Src1R); |
| 2484 } |
| 2485 _movt(DestR, Zero, FCC0); |
| 2486 _mov(Dest, DestR); |
| 2487 break; |
| 2488 } |
| 2489 case InstFcmp::Oge: { |
| 2490 if (Src0Ty == IceType_f32) { |
| 2491 _c_ult_s(Src0R, Src1R); |
| 2492 } else { |
| 2493 _c_ult_d(Src0R, Src1R); |
| 2494 } |
| 2495 _movt(DestR, Zero, FCC0); |
| 2496 _mov(Dest, DestR); |
| 2497 break; |
| 2498 } |
| 2499 case InstFcmp::Olt: { |
| 2500 if (Src0Ty == IceType_f32) { |
| 2501 _c_olt_s(Src0R, Src1R); |
| 2502 } else { |
| 2503 _c_olt_d(Src0R, Src1R); |
| 2504 } |
| 2505 _movf(DestR, Zero, FCC0); |
| 2506 _mov(Dest, DestR); |
| 2507 break; |
| 2508 } |
| 2509 case InstFcmp::Ole: { |
| 2510 if (Src0Ty == IceType_f32) { |
| 2511 _c_ole_s(Src0R, Src1R); |
| 2512 } else { |
| 2513 _c_ole_d(Src0R, Src1R); |
| 2514 } |
| 2515 _movf(DestR, Zero, FCC0); |
| 2516 _mov(Dest, DestR); |
| 2517 break; |
| 2518 } |
| 2519 case InstFcmp::One: { |
| 2520 if (Src0Ty == IceType_f32) { |
| 2521 _c_ueq_s(Src0R, Src1R); |
| 2522 } else { |
| 2523 _c_ueq_d(Src0R, Src1R); |
| 2524 } |
| 2525 _movt(DestR, Zero, FCC0); |
| 2526 _mov(Dest, DestR); |
| 2527 break; |
| 2528 } |
| 2529 case InstFcmp::Ord: { |
| 2530 if (Src0Ty == IceType_f32) { |
| 2531 _c_un_s(Src0R, Src1R); |
| 2532 } else { |
| 2533 _c_un_d(Src0R, Src1R); |
| 2534 } |
| 2535 _movt(DestR, Zero, FCC0); |
| 2536 _mov(Dest, DestR); |
| 2537 break; |
| 2538 } |
| 2539 case InstFcmp::Ueq: { |
| 2540 if (Src0Ty == IceType_f32) { |
| 2541 _c_ueq_s(Src0R, Src1R); |
| 2542 } else { |
| 2543 _c_ueq_d(Src0R, Src1R); |
| 2544 } |
| 2545 _movf(DestR, Zero, FCC0); |
| 2546 _mov(Dest, DestR); |
| 2547 break; |
| 2548 } |
| 2549 case InstFcmp::Ugt: { |
| 2550 if (Src0Ty == IceType_f32) { |
| 2551 _c_ole_s(Src0R, Src1R); |
| 2552 } else { |
| 2553 _c_ole_d(Src0R, Src1R); |
| 2554 } |
| 2555 _movt(DestR, Zero, FCC0); |
| 2556 _mov(Dest, DestR); |
| 2557 break; |
| 2558 } |
| 2559 case InstFcmp::Uge: { |
| 2560 if (Src0Ty == IceType_f32) { |
| 2561 _c_olt_s(Src0R, Src1R); |
| 2562 } else { |
| 2563 _c_olt_d(Src0R, Src1R); |
| 2564 } |
| 2565 _movt(DestR, Zero, FCC0); |
| 2566 _mov(Dest, DestR); |
| 2567 break; |
| 2568 } |
| 2569 case InstFcmp::Ult: { |
| 2570 if (Src0Ty == IceType_f32) { |
| 2571 _c_ult_s(Src0R, Src1R); |
| 2572 } else { |
| 2573 _c_ult_d(Src0R, Src1R); |
| 2574 } |
| 2575 _movf(DestR, Zero, FCC0); |
| 2576 _mov(Dest, DestR); |
| 2577 break; |
| 2578 } |
| 2579 case InstFcmp::Ule: { |
| 2580 if (Src0Ty == IceType_f32) { |
| 2581 _c_ule_s(Src0R, Src1R); |
| 2582 } else { |
| 2583 _c_ule_d(Src0R, Src1R); |
| 2584 } |
| 2585 _movf(DestR, Zero, FCC0); |
| 2586 _mov(Dest, DestR); |
| 2587 break; |
| 2588 } |
| 2589 case InstFcmp::Une: { |
| 2590 if (Src0Ty == IceType_f32) { |
| 2591 _c_eq_s(Src0R, Src1R); |
| 2592 } else { |
| 2593 _c_eq_d(Src0R, Src1R); |
| 2594 } |
| 2595 _movt(DestR, Zero, FCC0); |
| 2596 _mov(Dest, DestR); |
| 2597 break; |
| 2598 } |
| 2599 case InstFcmp::Uno: { |
| 2600 if (Src0Ty == IceType_f32) { |
| 2601 _c_un_s(Src0R, Src1R); |
| 2602 } else { |
| 2603 _c_un_d(Src0R, Src1R); |
| 2604 } |
| 2605 _movf(DestR, Zero, FCC0); |
| 2606 _mov(Dest, DestR); |
| 2607 break; |
| 2608 } |
| 2609 case InstFcmp::True: { |
| 2610 Context.insert<InstFakeUse>(Src0R); |
| 2611 Context.insert<InstFakeUse>(Src1R); |
| 2612 _addiu(DestR, Zero, 1); |
| 2613 _mov(Dest, DestR); |
| 2614 break; |
| 2615 } |
| 2616 } |
2440 } | 2617 } |
2441 | 2618 |
2442 void TargetMIPS32::lower64Icmp(const InstIcmp *Instr) { | 2619 void TargetMIPS32::lower64Icmp(const InstIcmp *Instr) { |
2443 UnimplementedLoweringError(this, Instr); | 2620 UnimplementedLoweringError(this, Instr); |
2444 return; | 2621 return; |
2445 } | 2622 } |
2446 | 2623 |
2447 void TargetMIPS32::lowerIcmp(const InstIcmp *Instr) { | 2624 void TargetMIPS32::lowerIcmp(const InstIcmp *Instr) { |
2448 auto *Src0 = Instr->getSrc(0); | 2625 auto *Src0 = Instr->getSrc(0); |
2449 auto *Src1 = Instr->getSrc(1); | 2626 auto *Src1 = Instr->getSrc(1); |
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3131 Str << "\t.set\t" | 3308 Str << "\t.set\t" |
3132 << "nomips16\n"; | 3309 << "nomips16\n"; |
3133 } | 3310 } |
3134 | 3311 |
3135 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM]; | 3312 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM]; |
3136 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM]; | 3313 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM]; |
3137 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM]; | 3314 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM]; |
3138 | 3315 |
3139 } // end of namespace MIPS32 | 3316 } // end of namespace MIPS32 |
3140 } // end of namespace Ice | 3317 } // end of namespace Ice |
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