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| 1 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===// | 1 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 /// | 9 /// |
| 10 /// \file | 10 /// \file |
| (...skipping 181 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 192 } | 192 } |
| 193 | 193 |
| 194 void _add_s(Variable *Dest, Variable *Src0, Variable *Src1) { | 194 void _add_s(Variable *Dest, Variable *Src0, Variable *Src1) { |
| 195 Context.insert<InstMIPS32Add_s>(Dest, Src0, Src1); | 195 Context.insert<InstMIPS32Add_s>(Dest, Src0, Src1); |
| 196 } | 196 } |
| 197 | 197 |
| 198 void _addiu(Variable *Dest, Variable *Src, uint32_t Imm) { | 198 void _addiu(Variable *Dest, Variable *Src, uint32_t Imm) { |
| 199 Context.insert<InstMIPS32Addiu>(Dest, Src, Imm); | 199 Context.insert<InstMIPS32Addiu>(Dest, Src, Imm); |
| 200 } | 200 } |
| 201 | 201 |
| 202 void _c_eq_d(Variable *Src0, Variable *Src1) { |
| 203 Context.insert<InstMIPS32C_eq_d>(Src0, Src1); |
| 204 } |
| 205 |
| 206 void _c_eq_s(Variable *Src0, Variable *Src1) { |
| 207 Context.insert<InstMIPS32C_eq_s>(Src0, Src1); |
| 208 } |
| 209 |
| 210 void _c_ole_d(Variable *Src0, Variable *Src1) { |
| 211 Context.insert<InstMIPS32C_ole_d>(Src0, Src1); |
| 212 } |
| 213 |
| 214 void _c_ole_s(Variable *Src0, Variable *Src1) { |
| 215 Context.insert<InstMIPS32C_ole_s>(Src0, Src1); |
| 216 } |
| 217 |
| 218 void _c_olt_d(Variable *Src0, Variable *Src1) { |
| 219 Context.insert<InstMIPS32C_olt_d>(Src0, Src1); |
| 220 } |
| 221 |
| 222 void _c_olt_s(Variable *Src0, Variable *Src1) { |
| 223 Context.insert<InstMIPS32C_olt_s>(Src0, Src1); |
| 224 } |
| 225 |
| 226 void _c_ueq_d(Variable *Src0, Variable *Src1) { |
| 227 Context.insert<InstMIPS32C_ueq_d>(Src0, Src1); |
| 228 } |
| 229 |
| 230 void _c_ueq_s(Variable *Src0, Variable *Src1) { |
| 231 Context.insert<InstMIPS32C_ueq_s>(Src0, Src1); |
| 232 } |
| 233 |
| 234 void _c_ule_d(Variable *Src0, Variable *Src1) { |
| 235 Context.insert<InstMIPS32C_ule_d>(Src0, Src1); |
| 236 } |
| 237 |
| 238 void _c_ule_s(Variable *Src0, Variable *Src1) { |
| 239 Context.insert<InstMIPS32C_ule_s>(Src0, Src1); |
| 240 } |
| 241 |
| 242 void _c_ult_d(Variable *Src0, Variable *Src1) { |
| 243 Context.insert<InstMIPS32C_ult_d>(Src0, Src1); |
| 244 } |
| 245 |
| 246 void _c_ult_s(Variable *Src0, Variable *Src1) { |
| 247 Context.insert<InstMIPS32C_ult_s>(Src0, Src1); |
| 248 } |
| 249 |
| 250 void _c_un_d(Variable *Src0, Variable *Src1) { |
| 251 Context.insert<InstMIPS32C_un_d>(Src0, Src1); |
| 252 } |
| 253 |
| 254 void _c_un_s(Variable *Src0, Variable *Src1) { |
| 255 Context.insert<InstMIPS32C_un_s>(Src0, Src1); |
| 256 } |
| 257 |
| 202 void _cvt_d_l(Variable *Dest, Variable *Src) { | 258 void _cvt_d_l(Variable *Dest, Variable *Src) { |
| 203 Context.insert<InstMIPS32Cvt_d_l>(Dest, Src); | 259 Context.insert<InstMIPS32Cvt_d_l>(Dest, Src); |
| 204 } | 260 } |
| 205 | 261 |
| 206 void _cvt_d_s(Variable *Dest, Variable *Src) { | 262 void _cvt_d_s(Variable *Dest, Variable *Src) { |
| 207 Context.insert<InstMIPS32Cvt_d_s>(Dest, Src); | 263 Context.insert<InstMIPS32Cvt_d_s>(Dest, Src); |
| 208 } | 264 } |
| 209 | 265 |
| 210 void _cvt_d_w(Variable *Dest, Variable *Src) { | 266 void _cvt_d_w(Variable *Dest, Variable *Src) { |
| 211 Context.insert<InstMIPS32Cvt_d_w>(Dest, Src); | 267 Context.insert<InstMIPS32Cvt_d_w>(Dest, Src); |
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| 272 } | 328 } |
| 273 | 329 |
| 274 void _mov_d(Variable *Dest, Variable *Src) { | 330 void _mov_d(Variable *Dest, Variable *Src) { |
| 275 Context.insert<InstMIPS32Mov_d>(Dest, Src); | 331 Context.insert<InstMIPS32Mov_d>(Dest, Src); |
| 276 } | 332 } |
| 277 | 333 |
| 278 void _mov_s(Variable *Dest, Variable *Src) { | 334 void _mov_s(Variable *Dest, Variable *Src) { |
| 279 Context.insert<InstMIPS32Mov_s>(Dest, Src); | 335 Context.insert<InstMIPS32Mov_s>(Dest, Src); |
| 280 } | 336 } |
| 281 | 337 |
| 338 void _movf(Variable *Src0, Variable *Src1, Operand *FCC) { |
| 339 Context.insert<InstMIPS32Movf>(Src0, Src1, FCC); |
| 340 } |
| 341 |
| 342 void _movt(Variable *Src0, Variable *Src1, Operand *FCC) { |
| 343 Context.insert<InstMIPS32Movt>(Src0, Src1, FCC); |
| 344 } |
| 345 |
| 282 void _mfc1(Variable *Dest, Variable *Src) { | 346 void _mfc1(Variable *Dest, Variable *Src) { |
| 283 Context.insert<InstMIPS32Mfc1>(Dest, Src); | 347 Context.insert<InstMIPS32Mfc1>(Dest, Src); |
| 284 } | 348 } |
| 285 | 349 |
| 286 void _mfhi(Variable *Dest, Operand *Src) { | 350 void _mfhi(Variable *Dest, Operand *Src) { |
| 287 Context.insert<InstMIPS32Mfhi>(Dest, Src); | 351 Context.insert<InstMIPS32Mfhi>(Dest, Src); |
| 288 } | 352 } |
| 289 | 353 |
| 290 void _mflo(Variable *Dest, Operand *Src) { | 354 void _mflo(Variable *Dest, Operand *Src) { |
| 291 Context.insert<InstMIPS32Mflo>(Dest, Src); | 355 Context.insert<InstMIPS32Mflo>(Dest, Src); |
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| 460 Variable *makeReg(Type Ty, RegNumT RegNum = RegNumT()); | 524 Variable *makeReg(Type Ty, RegNumT RegNum = RegNumT()); |
| 461 | 525 |
| 462 Variable *getZero() { | 526 Variable *getZero() { |
| 463 return getPhysicalRegister(RegMIPS32::Reg_ZERO, IceType_i32); | 527 return getPhysicalRegister(RegMIPS32::Reg_ZERO, IceType_i32); |
| 464 } | 528 } |
| 465 | 529 |
| 466 Variable *I32Reg(RegNumT RegNum = RegNumT()) { | 530 Variable *I32Reg(RegNumT RegNum = RegNumT()) { |
| 467 return makeReg(IceType_i32, RegNum); | 531 return makeReg(IceType_i32, RegNum); |
| 468 } | 532 } |
| 469 | 533 |
| 534 Variable *F32Reg(RegNumT RegNum = RegNumT()) { |
| 535 return makeReg(IceType_f32, RegNum); |
| 536 } |
| 537 |
| 538 Variable *F64Reg(RegNumT RegNum = RegNumT()) { |
| 539 return makeReg(IceType_f64, RegNum); |
| 540 } |
| 541 |
| 470 static Type stackSlotType(); | 542 static Type stackSlotType(); |
| 471 Variable *copyToReg(Operand *Src, RegNumT RegNum = RegNumT()); | 543 Variable *copyToReg(Operand *Src, RegNumT RegNum = RegNumT()); |
| 472 | 544 |
| 473 void unsetIfNonLeafFunc(); | 545 void unsetIfNonLeafFunc(); |
| 474 | 546 |
| 475 // Iterates over the CFG and determines the maximum outgoing stack arguments | 547 // Iterates over the CFG and determines the maximum outgoing stack arguments |
| 476 // bytes. This information is later used during addProlog() to pre-allocate | 548 // bytes. This information is later used during addProlog() to pre-allocate |
| 477 // the outargs area | 549 // the outargs area |
| 478 void findMaxStackOutArgsSize(); | 550 void findMaxStackOutArgsSize(); |
| 479 | 551 |
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| 726 explicit TargetHeaderMIPS32(GlobalContext *Ctx); | 798 explicit TargetHeaderMIPS32(GlobalContext *Ctx); |
| 727 | 799 |
| 728 private: | 800 private: |
| 729 ~TargetHeaderMIPS32() = default; | 801 ~TargetHeaderMIPS32() = default; |
| 730 }; | 802 }; |
| 731 | 803 |
| 732 } // end of namespace MIPS32 | 804 } // end of namespace MIPS32 |
| 733 } // end of namespace Ice | 805 } // end of namespace Ice |
| 734 | 806 |
| 735 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H | 807 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H |
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