[compiler] [wasm] Introduce Word32/64ReverseBytes as TF Optional Opcode

src/s390/disasm-s390.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 // A Disassembler object is used to disassemble a block of code instruction by
 // instruction. The default implementation of the NameConverter object can be
 // overriden to modify register names or to do symbol lookup on addresses.
 //
 // The example below will disassemble a block of code and print it to stdout.
 //
@@ skipping 716 matching lines @@
       break;
     case LTGR:
       Format(instr, "ltgr\t'r5,'r6");
       break;
     case LTDBR:
       Format(instr, "ltdbr\t'f5,'f6");
       break;
     case LTEBR:
       Format(instr, "ltebr\t'f5,'f6");
       break;
+    case LRVR:
+      Format(instr, "lrvr\t'r5,'r6");
+      break;
+    case LRVGR:
+      Format(instr, "lrvgr\t'r5,'r6");
+      break;
     case LGR:
       Format(instr, "lgr\t'r5,'r6");
       break;
     case LGDR:
       Format(instr, "lgdr\t'r5,'f6");
       break;
     case LGFR:
       Format(instr, "lgfr\t'r5,'r6");
       break;
     case LTGFR:
@@ skipping 431 matching lines @@
       break;
     case XG:
       Format(instr, "xg\t'r1,'d2('r2d,'r3)");
       break;
     case CG:
       Format(instr, "cg\t'r1,'d2('r2d,'r3)");
       break;
     case LB:
       Format(instr, "lb\t'r1,'d2('r2d,'r3)");
       break;
+    case LRVH:
+      Format(instr, "lrvh\t'r1,'d2('r2d,'r3)");
+      break;
+    case LRV:
+      Format(instr, "lrv\t'r1,'d2('r2d,'r3)");
+      break;
+    case LRVG:
+      Format(instr, "lrvg\t'r1,'d2('r2d,'r3)");
+      break;
     case LG:
       Format(instr, "lg\t'r1,'d2('r2d,'r3)");
       break;
     case LGF:
       Format(instr, "lgf\t'r1,'d2('r2d,'r3)");
       break;
     case LLGF:
       Format(instr, "llgf\t'r1,'d2('r2d,'r3)");
       break;
     case LY:
@@ skipping 52 matching lines @@
       break;
     case CLG:
       Format(instr, "clg\t'r1,'d2('r2d,'r3)");
       break;
     case BCTG:
       Format(instr, "bctg\t'r1,'d2('r2d,'r3)");
       break;
     case STY:
       Format(instr, "sty\t'r1,'d2('r2d,'r3)");
       break;
+    case STRVH:
+      Format(instr, "strvh\t'r1,'d2('r2d,'r3)");
+      break;
+    case STRV:
+      Format(instr, "strv\t'r1,'d2('r2d,'r3)");
+      break;
+    case STRVG:
+      Format(instr, "strvg\t'r1,'d2('r2d,'r3)");
+      break;
     case STG:
       Format(instr, "stg\t'r1,'d2('r2d,'r3)");
       break;
     case ICY:
       Format(instr, "icy\t'r1,'d2('r2d,'r3)");
       break;
     case MVC:
       Format(instr, "mvc\t'd3('i8,'r3),'d4('r7)");
       break;
     case MVHI:
@@ skipping 142 matching lines @@
     byte* prev_pc = pc;
     pc += d.InstructionDecode(buffer, pc);
     v8::internal::PrintF(f, "%p    %08x      %s\n", static_cast<void*>(prev_pc),
                          *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
   }
 }
 
 }  // namespace disasm
 
 #endif  // V8_TARGET_ARCH_S390