OLD | NEW |
1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include <limits.h> // For LONG_MIN, LONG_MAX. | 5 #include <limits.h> // For LONG_MIN, LONG_MAX. |
6 | 6 |
7 #if V8_TARGET_ARCH_MIPS | 7 #if V8_TARGET_ARCH_MIPS |
8 | 8 |
9 #include "src/base/bits.h" | 9 #include "src/base/bits.h" |
10 #include "src/base/division-by-constant.h" | 10 #include "src/base/division-by-constant.h" |
(...skipping 1385 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1396 IsMipsArchVariant(kLoongson)); | 1396 IsMipsArchVariant(kLoongson)); |
1397 mfc1(scratch, fd); | 1397 mfc1(scratch, fd); |
1398 Usw(scratch, MemOperand(rs.rm(), rs.offset() + Register::kMantissaOffset)); | 1398 Usw(scratch, MemOperand(rs.rm(), rs.offset() + Register::kMantissaOffset)); |
1399 Mfhc1(scratch, fd); | 1399 Mfhc1(scratch, fd); |
1400 Usw(scratch, MemOperand(rs.rm(), rs.offset() + Register::kExponentOffset)); | 1400 Usw(scratch, MemOperand(rs.rm(), rs.offset() + Register::kExponentOffset)); |
1401 } | 1401 } |
1402 } | 1402 } |
1403 | 1403 |
1404 | 1404 |
1405 void MacroAssembler::li(Register dst, Handle<Object> value, LiFlags mode) { | 1405 void MacroAssembler::li(Register dst, Handle<Object> value, LiFlags mode) { |
1406 AllowDeferredHandleDereference smi_check; | 1406 li(dst, Operand(value), mode); |
1407 if (value->IsSmi()) { | |
1408 li(dst, Operand(value), mode); | |
1409 } else { | |
1410 DCHECK(value->IsHeapObject()); | |
1411 if (isolate()->heap()->InNewSpace(*value)) { | |
1412 Handle<Cell> cell = isolate()->factory()->NewCell(value); | |
1413 li(dst, Operand(cell)); | |
1414 lw(dst, FieldMemOperand(dst, Cell::kValueOffset)); | |
1415 } else { | |
1416 li(dst, Operand(value)); | |
1417 } | |
1418 } | |
1419 } | 1407 } |
1420 | 1408 |
1421 | 1409 |
1422 void MacroAssembler::li(Register rd, Operand j, LiFlags mode) { | 1410 void MacroAssembler::li(Register rd, Operand j, LiFlags mode) { |
1423 DCHECK(!j.is_reg()); | 1411 DCHECK(!j.is_reg()); |
1424 BlockTrampolinePoolScope block_trampoline_pool(this); | 1412 BlockTrampolinePoolScope block_trampoline_pool(this); |
1425 if (!MustUseReg(j.rmode_) && mode == OPTIMIZE_SIZE) { | 1413 if (!MustUseReg(j.rmode_) && mode == OPTIMIZE_SIZE) { |
1426 // Normal load of an immediate value which does not need Relocation Info. | 1414 // Normal load of an immediate value which does not need Relocation Info. |
1427 if (is_int16(j.imm32_)) { | 1415 if (is_int16(j.imm32_)) { |
1428 addiu(rd, zero_reg, j.imm32_); | 1416 addiu(rd, zero_reg, j.imm32_); |
(...skipping 5445 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
6874 if (mag.shift > 0) sra(result, result, mag.shift); | 6862 if (mag.shift > 0) sra(result, result, mag.shift); |
6875 srl(at, dividend, 31); | 6863 srl(at, dividend, 31); |
6876 Addu(result, result, Operand(at)); | 6864 Addu(result, result, Operand(at)); |
6877 } | 6865 } |
6878 | 6866 |
6879 | 6867 |
6880 } // namespace internal | 6868 } // namespace internal |
6881 } // namespace v8 | 6869 } // namespace v8 |
6882 | 6870 |
6883 #endif // V8_TARGET_ARCH_MIPS | 6871 #endif // V8_TARGET_ARCH_MIPS |
OLD | NEW |