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Issue 204343005: MIPS: Reland "Add out-of-line constant pool support to Arm." (Closed) Base URL: https://github.com/v8/v8.git@gbl
Patch Set: Created 6 years, 9 months ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are 5 // modification, are permitted provided that the following conditions are
6 // met: 6 // met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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30 30
31 // The original source code covered by the above license above has been 31 // The original source code covered by the above license above has been
32 // modified significantly by Google Inc. 32 // modified significantly by Google Inc.
33 // Copyright 2012 the V8 project authors. All rights reserved. 33 // Copyright 2012 the V8 project authors. All rights reserved.
34 34
35 35
36 #ifndef V8_MIPS_ASSEMBLER_MIPS_H_ 36 #ifndef V8_MIPS_ASSEMBLER_MIPS_H_
37 #define V8_MIPS_ASSEMBLER_MIPS_H_ 37 #define V8_MIPS_ASSEMBLER_MIPS_H_
38 38
39 #include <stdio.h> 39 #include <stdio.h>
40
40 #include "assembler.h" 41 #include "assembler.h"
41 #include "constants-mips.h" 42 #include "constants-mips.h"
42 #include "serialize.h" 43 #include "serialize.h"
43 44
44 namespace v8 { 45 namespace v8 {
45 namespace internal { 46 namespace internal {
46 47
47 // CPU Registers. 48 // CPU Registers.
48 // 49 //
49 // 1) We would prefer to use an enum, but enum values are assignment- 50 // 1) We would prefer to use an enum, but enum values are assignment-
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998 static bool IsSw(Instr instr); 999 static bool IsSw(Instr instr);
999 static Instr SetSwOffset(Instr instr, int16_t offset); 1000 static Instr SetSwOffset(Instr instr, int16_t offset);
1000 static bool IsAddImmediate(Instr instr); 1001 static bool IsAddImmediate(Instr instr);
1001 static Instr SetAddImmediateOffset(Instr instr, int16_t offset); 1002 static Instr SetAddImmediateOffset(Instr instr, int16_t offset);
1002 1003
1003 static bool IsAndImmediate(Instr instr); 1004 static bool IsAndImmediate(Instr instr);
1004 static bool IsEmittedConstant(Instr instr); 1005 static bool IsEmittedConstant(Instr instr);
1005 1006
1006 void CheckTrampolinePool(); 1007 void CheckTrampolinePool();
1007 1008
1009 // Allocate a constant pool of the correct size for the generated code.
1010 MaybeObject* AllocateConstantPool(Heap* heap);
1011
1012 // Generate the constant pool for the generated code.
1013 void PopulateConstantPool(ConstantPoolArray* constant_pool);
1014
1008 protected: 1015 protected:
1009 // Relocation for a type-recording IC has the AST id added to it. This 1016 // Relocation for a type-recording IC has the AST id added to it. This
1010 // member variable is a way to pass the information from the call site to 1017 // member variable is a way to pass the information from the call site to
1011 // the relocation info. 1018 // the relocation info.
1012 TypeFeedbackId recorded_ast_id_; 1019 TypeFeedbackId recorded_ast_id_;
1013 1020
1014 int32_t buffer_space() const { return reloc_info_writer.pos() - pc_; } 1021 int32_t buffer_space() const { return reloc_info_writer.pos() - pc_; }
1015 1022
1016 // Decode branch instruction at pos and return branch target pos. 1023 // Decode branch instruction at pos and return branch target pos.
1017 int target_at(int32_t pos); 1024 int target_at(int32_t pos);
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1268 class EnsureSpace BASE_EMBEDDED { 1275 class EnsureSpace BASE_EMBEDDED {
1269 public: 1276 public:
1270 explicit EnsureSpace(Assembler* assembler) { 1277 explicit EnsureSpace(Assembler* assembler) {
1271 assembler->CheckBuffer(); 1278 assembler->CheckBuffer();
1272 } 1279 }
1273 }; 1280 };
1274 1281
1275 } } // namespace v8::internal 1282 } } // namespace v8::internal
1276 1283
1277 #endif // V8_ARM_ASSEMBLER_MIPS_H_ 1284 #endif // V8_ARM_ASSEMBLER_MIPS_H_
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