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Side by Side Diff: src/mips/lithium-codegen-mips.h

Issue 20407002: MIPS: Adding Smi support to Add, Sub, Mul, and Bitwise (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 7 years, 5 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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107 // LOperand is loaded into scratch, unless already a register. 107 // LOperand is loaded into scratch, unless already a register.
108 Register EmitLoadRegister(LOperand* op, Register scratch); 108 Register EmitLoadRegister(LOperand* op, Register scratch);
109 109
110 // LOperand must be a double register. 110 // LOperand must be a double register.
111 DoubleRegister ToDoubleRegister(LOperand* op) const; 111 DoubleRegister ToDoubleRegister(LOperand* op) const;
112 112
113 // LOperand is loaded into dbl_scratch, unless already a double register. 113 // LOperand is loaded into dbl_scratch, unless already a double register.
114 DoubleRegister EmitLoadDoubleRegister(LOperand* op, 114 DoubleRegister EmitLoadDoubleRegister(LOperand* op,
115 FloatRegister flt_scratch, 115 FloatRegister flt_scratch,
116 DoubleRegister dbl_scratch); 116 DoubleRegister dbl_scratch);
117 int ToInteger32(LConstantOperand* op) const; 117 int ToRepresentation(LConstantOperand* op, const Representation& r) const;
118 int32_t ToInteger32(LConstantOperand* op) const;
118 Smi* ToSmi(LConstantOperand* op) const; 119 Smi* ToSmi(LConstantOperand* op) const;
119 double ToDouble(LConstantOperand* op) const; 120 double ToDouble(LConstantOperand* op) const;
120 Operand ToOperand(LOperand* op); 121 Operand ToOperand(LOperand* op);
121 MemOperand ToMemOperand(LOperand* op) const; 122 MemOperand ToMemOperand(LOperand* op) const;
122 // Returns a MemOperand pointing to the high word of a DoubleStackSlot. 123 // Returns a MemOperand pointing to the high word of a DoubleStackSlot.
123 MemOperand ToHighMemOperand(LOperand* op) const; 124 MemOperand ToHighMemOperand(LOperand* op) const;
124 125
125 bool IsInteger32(LConstantOperand* op) const; 126 bool IsInteger32(LConstantOperand* op) const;
126 bool IsSmi(LConstantOperand* op) const; 127 bool IsSmi(LConstantOperand* op) const;
127 Handle<Object> ToHandle(LConstantOperand* op) const; 128 Handle<Object> ToHandle(LConstantOperand* op) const;
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504 LCodeGen* codegen_; 505 LCodeGen* codegen_;
505 Label entry_; 506 Label entry_;
506 Label exit_; 507 Label exit_;
507 Label* external_exit_; 508 Label* external_exit_;
508 int instruction_index_; 509 int instruction_index_;
509 }; 510 };
510 511
511 } } // namespace v8::internal 512 } } // namespace v8::internal
512 513
513 #endif // V8_MIPS_LITHIUM_CODEGEN_MIPS_H_ 514 #endif // V8_MIPS_LITHIUM_CODEGEN_MIPS_H_
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