Implements far branch targets for MIPS.

runtime/vm/intrinsifier_mips.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_MIPS.
 #if defined(TARGET_ARCH_MIPS)
 
 #include "vm/intrinsifier.h"
 
 #include "vm/assembler.h"
@@ skipping 195 matching lines @@
     __ beq(T2, T7, &checked_ok);
 
     __ lw(T1, Address(SP, 2 * kWordSize));  // Array.
     __ lw(T1, FieldAddress(T1, type_args_field_offset));
 
     // T1: Type arguments of array.
     __ beq(T1, T7, &checked_ok);
 
     // Check if it's dynamic.
     // For now handle only TypeArguments and bail out if InstantiatedTypeArgs.
-    __ LoadClassId(TMP, T1);
-    __ BranchNotEqual(TMP, kTypeArgumentsCid, &fall_through);
+    __ LoadClassId(CMPRES1, T1);
+    __ BranchNotEqual(CMPRES1, kTypeArgumentsCid, &fall_through);
 
     // Get type at index 0.
     __ lw(T0, FieldAddress(T1, TypeArguments::type_at_offset(0)));
     __ BranchEqual(T0, Type::ZoneHandle(Type::DynamicType()), &checked_ok);
 
     // Check for int and num.
     __ andi(CMPRES, T2, Immediate(kSmiTagMask));
     __ bne(CMPRES, ZR, &fall_through);  // Non-smi value.
 
     __ BranchEqual(T0, Type::ZoneHandle(Type::IntType()), &checked_ok);
@@ skipping 189 matching lines @@
 // On stack: growable array (+1), data (+0).
 bool Intrinsifier::GrowableArray_setData(Assembler* assembler) {
   if (FLAG_enable_type_checks) {
     return false;
   }
   Label fall_through;
   __ lw(T1, Address(SP, 0 * kWordSize));  // Data.
   // Check that data is an ObjectArray.
   __ andi(CMPRES, T1, Immediate(kSmiTagMask));
   __ beq(CMPRES, ZR, &fall_through);  // Data is Smi.
-  __ LoadClassId(TMP, T1);
-  __ BranchNotEqual(TMP, kArrayCid, &fall_through);
+  __ LoadClassId(CMPRES1, T1);
+  __ BranchNotEqual(CMPRES1, kArrayCid, &fall_through);
   __ lw(T0, Address(SP, 1 * kWordSize));  // Growable array.
   __ StoreIntoObject(T0,
                      FieldAddress(T0, GrowableObjectArray::data_offset()),
                      T1);
   __ Ret();
   __ Bind(&fall_through);
   return false;
 }
 
 
@@ skipping 419 matching lines @@
   ASSERT(kSmiTag == 0);
   Label fall_through, overflow;
 
   TestBothArgumentsSmis(assembler, &fall_through);
   __ BranchUnsignedGreater(T0, Smi::RawValue(Smi::kBits), &fall_through);
   __ SmiUntag(T0);
 
   // Check for overflow by shifting left and shifting back arithmetically.
   // If the result is different from the original, there was overflow.
   __ sllv(TMP, T1, T0);
-  __ srav(TMP, TMP, T0);
-  __ bne(TMP, T1, &overflow);
+  __ srav(CMPRES1, TMP, T0);
+  __ bne(CMPRES1, T1, &overflow);
 
   // No overflow, result in V0.
   __ Ret();
   __ delay_slot()->sllv(V0, T1, T0);
 
   __ Bind(&overflow);
   // Arguments are Smi but the shift produced an overflow to Mint.
   __ bltz(T1, &fall_through);
   __ SmiUntag(T1);
 
@@ skipping 33 matching lines @@
   __ andi(CMPRES, reg, Immediate(kSmiTagMask));
   __ bne(CMPRES, ZR, &not_smi);
   __ SmiUntag(reg);
 
   // Sign extend to 64 bit
   __ mov(res_lo, reg);
   __ b(&done);
   __ delay_slot()->sra(res_hi, reg, 31);
 
   __ Bind(&not_smi);
-  __ LoadClassId(TMP, reg);
-  __ BranchNotEqual(TMP, kMintCid, not_smi_or_mint);
+  __ LoadClassId(CMPRES1, reg);
+  __ BranchNotEqual(CMPRES1, kMintCid, not_smi_or_mint);
 
   // Mint.
   __ lw(res_lo, FieldAddress(reg, Mint::value_offset()));
   __ lw(res_hi, FieldAddress(reg, Mint::value_offset() + kWordSize));
   __ Bind(&done);
   return;
 }
 
 
 static bool CompareIntegers(Assembler* assembler, Condition true_condition) {
@@ skipping 119 matching lines @@
   Label receiver_not_smi;
   __ Bind(&check_for_mint);
 
   __ andi(CMPRES, T1, Immediate(kSmiTagMask));
   __ bne(CMPRES, ZR, &receiver_not_smi);  // Check receiver.
 
   // Left (receiver) is Smi, return false if right is not Double.
   // Note that an instance of Mint or Bigint never contains a value that can be
   // represented by Smi.
 
-  __ LoadClassId(TMP, T0);
-  __ BranchEqual(TMP, kDoubleCid, &fall_through);
+  __ LoadClassId(CMPRES1, T0);
+  __ BranchEqual(CMPRES1, kDoubleCid, &fall_through);
   __ LoadObject(V0, Bool::False());  // Smi == Mint -> false.
   __ Ret();
 
   __ Bind(&receiver_not_smi);
   // T1:: receiver.
 
-  __ LoadClassId(TMP, T1);
-  __ BranchNotEqual(TMP, kMintCid, &fall_through);
+  __ LoadClassId(CMPRES1, T1);
+  __ BranchNotEqual(CMPRES1, kMintCid, &fall_through);
   // Receiver is Mint, return false if right is Smi.
   __ andi(CMPRES, T0, Immediate(kSmiTagMask));
   __ bne(CMPRES, ZR, &fall_through);
   __ LoadObject(V0, Bool::False());
   __ Ret();
   // TODO(srdjan): Implement Mint == Mint comparison.
 
   __ Bind(&fall_through);
   return false;
 }
@@ skipping 37 matching lines @@
 
 // Check if the last argument is a double, jump to label 'is_smi' if smi
 // (easy to convert to double), otherwise jump to label 'not_double_smi',
 // Returns the last argument in T0.
 static void TestLastArgumentIsDouble(Assembler* assembler,
                                      Label* is_smi,
                                      Label* not_double_smi) {
   __ lw(T0, Address(SP, 0 * kWordSize));
   __ andi(CMPRES, T0, Immediate(kSmiTagMask));
   __ beq(CMPRES, ZR, is_smi);
-  __ LoadClassId(TMP, T0);
-  __ BranchNotEqual(TMP, kDoubleCid, not_double_smi);
+  __ LoadClassId(CMPRES1, T0);
+  __ BranchNotEqual(CMPRES1, kDoubleCid, not_double_smi);
   // Fall through with Double in T0.
 }
 
 
 // Both arguments on stack, arg0 (left) is a double, arg1 (right) is of unknown
 // type. Return true or false object in the register V0. Any NaN argument
 // returns false. Any non-double arg1 causes control flow to fall through to the
 // slow case (compiled method body).
 static bool CompareDoubles(Assembler* assembler, Condition true_condition) {
   Label is_smi, double_op, no_NaN, fall_through;
@@ skipping 368 matching lines @@
 
   __ lw(T1, Address(SP, 0 * kWordSize));  // Index.
   __ lw(T0, Address(SP, 1 * kWordSize));  // String.
 
   // Checks.
   __ andi(CMPRES, T1, Immediate(kSmiTagMask));
   __ bne(T1, ZR, &fall_through);  // Index is not a Smi.
   __ lw(T2, FieldAddress(T0, String::length_offset()));  // Range check.
   // Runtime throws exception.
   __ BranchUnsignedGreaterEqual(T1, T2, &fall_through);
-  __ LoadClassId(TMP1, T0);  // Class ID check.
-  __ BranchNotEqual(TMP1, kOneByteStringCid, &try_two_byte_string);
+  __ LoadClassId(CMPRES1, T0);  // Class ID check.
+  __ BranchNotEqual(CMPRES1, kOneByteStringCid, &try_two_byte_string);
 
   // Grab byte and return.
   __ SmiUntag(T1);
   __ addu(T2, T0, T1);
   __ lbu(V0, FieldAddress(T2, OneByteString::data_offset()));
   __ Ret();
   __ delay_slot()->SmiTag(V0);
 
   __ Bind(&try_two_byte_string);
-  __ BranchNotEqual(TMP1, kTwoByteStringCid, &fall_through);
+  __ BranchNotEqual(CMPRES1, kTwoByteStringCid, &fall_through);
   ASSERT(kSmiTagShift == 1);
   __ addu(T2, T0, T1);
   __ lhu(V0, FieldAddress(T2, OneByteString::data_offset()));
   __ Ret();
   __ delay_slot()->SmiTag(V0);
 
   __ Bind(&fall_through);
   return false;
 }
 
@@ skipping 43 matching lines @@
   // Add to hash code: (hash_ is uint32)
   // hash_ += ch;
   // hash_ += hash_ << 10;
   // hash_ ^= hash_ >> 6;
   // Get one characters (ch).
   __ Bind(&loop);
   __ lbu(T5, Address(T3));
   // T5: ch.
   __ addiu(T3, T3, Immediate(1));
   __ addu(V0, V0, T5);
-  __ sll(TMP, V0, 10);
-  __ addu(V0, V0, TMP);
-  __ srl(TMP, V0, 6);
+  __ sll(T6, V0, 10);
+  __ addu(V0, V0, T6);
+  __ srl(T6, V0, 6);
   __ bne(T3, T4, &loop);
-  __ delay_slot()->xor_(V0, V0, TMP);
+  __ delay_slot()->xor_(V0, V0, T6);
 
   // Finalize.
   // hash_ += hash_ << 3;
   // hash_ ^= hash_ >> 11;
   // hash_ += hash_ << 15;
-  __ sll(TMP, V0, 3);
-  __ addu(V0, V0, TMP);
-  __ srl(TMP, V0, 11);
-  __ xor_(V0, V0, TMP);
-  __ sll(TMP, V0, 15);
-  __ addu(V0, V0, TMP);
+  __ sll(T6, V0, 3);
+  __ addu(V0, V0, T6);
+  __ srl(T6, V0, 11);
+  __ xor_(V0, V0, T6);
+  __ sll(T6, V0, 15);
+  __ addu(V0, V0, T6);
   // hash_ = hash_ & ((static_cast<intptr_t>(1) << bits) - 1);
-  __ LoadImmediate(TMP, (static_cast<intptr_t>(1) << String::kHashBits) - 1);
-  __ and_(V0, V0, TMP);
+  __ LoadImmediate(T6, (static_cast<intptr_t>(1) << String::kHashBits) - 1);
+  __ and_(V0, V0, T6);
   __ Bind(&done);
 
   __ LoadImmediate(T2, 1);
   __ movz(V0, T2, V0);  // If V0 is 0, set to 1.
   __ SmiTag(V0);
 
   __ Ret();
   __ delay_slot()->sw(V0, FieldAddress(T1, String::hash_offset()));
   return true;
 }
@@ skipping 150 matching lines @@
   __ Bind(&ok);
   __ Ret();
 
   __ Bind(&fall_through);
   return false;
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_MIPS