Implements far branch targets for MIPS.

runtime/vm/flow_graph_compiler_mips.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_MIPS.
 #if defined(TARGET_ARCH_MIPS)
 
 #include "vm/flow_graph_compiler.h"
 
 #include "lib/error.h"
@@ skipping 1034 matching lines @@
   __ sll(T2, T2, 1);  // T2 is a Smi.
 
   __ Comment("Null arguments loop");
   Label null_args_loop, null_args_loop_exit;
   __ blez(T2, &null_args_loop_exit);
   __ delay_slot()->addiu(T1, FP,
                          Immediate((kParamEndSlotFromFp + 1) * kWordSize));
   __ Bind(&null_args_loop);
   __ addiu(T2, T2, Immediate(-kWordSize));
   __ addu(T3, T1, T2);
-  __ LoadImmediate(TMP, reinterpret_cast<int32_t>(Object::null()));
+  __ LoadImmediate(T5, reinterpret_cast<int32_t>(Object::null()));
   __ bgtz(T2, &null_args_loop);
-  __ delay_slot()->sw(TMP, Address(T3));
+  __ delay_slot()->sw(T5, Address(T3));
   __ Bind(&null_args_loop_exit);
 }
 
 
 void FlowGraphCompiler::GenerateInlinedGetter(intptr_t offset) {
   // RA: return address.
   // SP: receiver.
   // Sequence node has one return node, its input is load field node.
   __ lw(V0, Address(SP, 0 * kWordSize));
   __ lw(V0, Address(V0, offset - kHeapObjectTag));
   __ Ret();
 }
 
 
 void FlowGraphCompiler::GenerateInlinedSetter(intptr_t offset) {
   // RA: return address.
   // SP+1: receiver.
   // SP+0: value.
   // Sequence node has one store node and one return NULL node.
   __ lw(T0, Address(SP, 1 * kWordSize));  // Receiver.
   __ lw(T1, Address(SP, 0 * kWordSize));  // Value.
   __ StoreIntoObject(T0, FieldAddress(T0, offset), T1);
-  __ LoadImmediate(TMP, reinterpret_cast<int32_t>(Object::null()));
+  __ LoadImmediate(V0, reinterpret_cast<int32_t>(Object::null()));
   __ Ret();
-  __ delay_slot()->mov(V0, TMP);
 }
 
 
 void FlowGraphCompiler::EmitFrameEntry() {
   const Function& function = parsed_function().function();
   if (CanOptimizeFunction() &&
       function.is_optimizable() &&
       (!is_optimizing() || may_reoptimize())) {
     const Register function_reg = T0;
 
-    Label next;
-    // The pool pointer is not setup before entering the Dart frame.
-    __ mov(TMP1, RA);  // Save RA.
-    __ bal(&next);  // Branch and link to next instruction to get PC in RA.
-    __ delay_slot()->mov(T2, RA);  // Save PC of the following mov.
+    __ GetNextPC(T2, TMP);
+
     // Calculate offset of pool pointer from the PC.
     const intptr_t object_pool_pc_dist =
        Instructions::HeaderSize() - Instructions::object_pool_offset() +
-       assembler()->CodeSize();
-    __ Bind(&next);
-    __ mov(RA, TMP1);  // Restore RA.
+       assembler()->CodeSize() - 1 * Instr::kInstrSize;
+
     // Preserve PP of caller.
     __ mov(T1, PP);
     // Temporarily setup pool pointer for this dart function.
     __ lw(PP, Address(T2, -object_pool_pc_dist));
     // Load function object from object pool.
     __ LoadObject(function_reg, function);  // Uses PP.
     // Restore PP of caller.
     __ mov(PP, T1);
 
     // Patch point is after the eventually inlined function object.
@@ skipping 365 matching lines @@
       __ BranchLink(&StubCode::UnoptimizedIdenticalWithNumberCheckLabel());
     }
     AddCurrentDescriptor(PcDescriptors::kRuntimeCall,
                          Isolate::kNoDeoptId,
                          token_pos);
     __ TraceSimMsg("EqualityRegConstCompare return");
     __ lw(reg, Address(SP, 1 * kWordSize));  // Restore 'reg'.
     __ addiu(SP, SP, Immediate(2 * kWordSize));  // Discard constant.
     return;
   }
-  __ CompareObject(CMPRES, TMP1, reg, obj);
+  __ CompareObject(CMPRES1, CMPRES2, reg, obj);
 }
 
 
 void FlowGraphCompiler::EmitEqualityRegRegCompare(Register left,
                                                   Register right,
                                                   bool needs_number_check,
                                                   intptr_t token_pos) {
   __ TraceSimMsg("EqualityRegRegCompare");
   __ Comment("EqualityRegRegCompare");
   if (needs_number_check) {
     __ addiu(SP, SP, Immediate(-2 * kWordSize));
     __ sw(left, Address(SP, 1 * kWordSize));
     __ sw(right, Address(SP, 0 * kWordSize));
     if (is_optimizing()) {
       __ BranchLink(&StubCode::OptimizedIdenticalWithNumberCheckLabel());
     } else {
       __ BranchLink(&StubCode::UnoptimizedIdenticalWithNumberCheckLabel());
     }
     AddCurrentDescriptor(PcDescriptors::kRuntimeCall,
                          Isolate::kNoDeoptId,
                          token_pos);
     __ TraceSimMsg("EqualityRegRegCompare return");
     // Stub returns result in CMPRES. If it is 0, then left and right are equal.
     __ lw(right, Address(SP, 0 * kWordSize));
     __ lw(left, Address(SP, 1 * kWordSize));
     __ addiu(SP, SP, Immediate(2 * kWordSize));
   } else {
-    __ slt(CMPRES, left, right);
-    __ slt(TMP1, right, left);
+    __ slt(CMPRES1, left, right);
+    __ slt(CMPRES2, right, left);
   }
 }
 
 
 // Implement equality spec: if any of the arguments is null do identity check.
 // Fallthrough calls super equality.
 void FlowGraphCompiler::EmitSuperEqualityCallPrologue(Register result,
                                                       Label* skip_call) {
   Label check_identity, is_false, fall_through;
   __ TraceSimMsg("SuperEqualityCallPrologue");
   __ lw(result, Address(SP, 0 * kWordSize));  // Load right operand.
-  __ lw(TMP1, Address(SP, 1 * kWordSize));  // Load left operand.
-  __ LoadImmediate(CMPRES, reinterpret_cast<int32_t>(Object::null()));
-  __ beq(result, CMPRES, &check_identity);  // Is right null?
-  __ bne(TMP1, CMPRES, &fall_through);  // If right is non-null, check left.
+  __ lw(CMPRES1, Address(SP, 1 * kWordSize));  // Load left operand.
+  __ LoadImmediate(TMP, reinterpret_cast<int32_t>(Object::null()));
+  __ beq(result, TMP, &check_identity);  // Is right null?
+  __ LoadImmediate(TMP, reinterpret_cast<int32_t>(Object::null()));
+  __ bne(TMP, CMPRES1, &fall_through);  // If right is non-null, check left.
 
   __ Bind(&check_identity);
-  __ bne(result, TMP1, &is_false);
+  __ bne(result, CMPRES1, &is_false);
   __ LoadObject(result, Bool::True());
   __ Drop(2);
   __ b(skip_call);
   __ Bind(&is_false);
   __ LoadObject(result, Bool::False());
   __ Drop(2);
   __ b(skip_call);
   __ Bind(&fall_through);
 }
 
@@ skipping 139 matching lines @@
     case GE: assembler()->coled(right, left); break;
     default: {
       // Should only passing the above conditions to this function.
       UNREACHABLE();
       break;
     }
   }
 
   assembler()->LoadImmediate(TMP, 1);
   if (true_condition == NE) {
-    assembler()->movf(CMPRES, ZR);
-    assembler()->movt(CMPRES, TMP);
+    assembler()->movf(CMPRES1, ZR);
+    assembler()->movt(CMPRES1, TMP);
   } else {
-    assembler()->movf(CMPRES, TMP);
-    assembler()->movt(CMPRES, ZR);
+    assembler()->movf(CMPRES1, TMP);
+    assembler()->movt(CMPRES1, ZR);
   }
-  assembler()->mov(TMP, ZR);
+  assembler()->mov(CMPRES2, ZR);
 
-  // EmitBranchOnCondition expects ordering to be described by CMPRES, TMP1.
+  // EmitBranchOnCondition expects ordering to be described by CMPRES, CMPRES2.
   branch->EmitBranchOnCondition(this, EQ);
 }
 
 
 void FlowGraphCompiler::EmitDoubleCompareBool(Condition true_condition,
                                               FpuRegister left,
                                               FpuRegister right,
                                               Register result) {
   Label done;
   __ Comment("DoubleCompareBool");
@@ skipping 284 matching lines @@
   __ AddImmediate(SP, kDoubleSize);
 }
 
 
 #undef __
 
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_MIPS