Implements far branch targets for MIPS.

runtime/vm/assembler_mips.h

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_MIPS_H_
 #define VM_ASSEMBLER_MIPS_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_mips.h directly; use assembler.h instead.
 #endif
 
 #include "platform/assert.h"
 #include "platform/utils.h"
 #include "vm/constants_mips.h"
 #include "vm/simulator.h"
 
 // References to documentation in this file refer to:
 // "MIPS® Architecture For Programmers Volume I-A:
 //   Introduction to the MIPS32® Architecture" in short "VolI-A"
 // and
 // "MIPS® Architecture For Programmers Volume II-A:
 //   The MIPS32® Instruction Set" in short "VolII-A"
 namespace dart {
 
+DECLARE_FLAG(bool, mips_far_branches);

[regis, 2013/07/26 22:30:38]

'mips_' is not really needed, but since I understand it is a temporary flag, it
does not matter.

[zra, 2013/07/26 23:29:03]

Changed to use_far_branches, and I'll use the same flag for ARM.

+
 // Forward declarations.
 class RuntimeEntry;
 
 class Immediate : public ValueObject {
  public:
   explicit Immediate(int32_t value) : value_(value) { }
 
   Immediate(const Immediate& other) : ValueObject(), value_(other.value_) { }
   Immediate& operator=(const Immediate& other) {
     value_ = other.value_;
@@ skipping 812 matching lines @@
       LoadImmediate(TMP1, value);
       addu(rd, rs, TMP1);
     }
   }
 
   void AddImmediate(Register rd, int32_t value) {
     AddImmediate(rd, rd, value);
   }
 
   void BranchEqual(Register rd, int32_t value, Label* l) {
-    ASSERT(rd != CMPRES);
-    LoadImmediate(CMPRES, value);
-    beq(rd, CMPRES, l);
+    ASSERT(rd != CMPRES2);
+    LoadImmediate(CMPRES2, value);
+    beq(rd, CMPRES2, l);
   }
 
   void BranchEqual(Register rd, const Object& object, Label* l) {
-    ASSERT(rd != CMPRES);
-    LoadObject(CMPRES, object);
-    beq(rd, CMPRES, l);
+    ASSERT(rd != CMPRES2);
+    LoadObject(CMPRES2, object);
+    beq(rd, CMPRES2, l);
   }
 
   void BranchNotEqual(Register rd, int32_t value, Label* l) {
-    ASSERT(rd != CMPRES);
-    LoadImmediate(CMPRES, value);
-    bne(rd, CMPRES, l);
+    ASSERT(rd != CMPRES2);
+    LoadImmediate(CMPRES2, value);
+    bne(rd, CMPRES2, l);
   }
 
   void BranchNotEqual(Register rd, const Object& object, Label* l) {
-    ASSERT(rd != CMPRES);
-    LoadObject(CMPRES, object);
-    bne(rd, CMPRES, l);
+    ASSERT(rd != CMPRES2);
+    LoadObject(CMPRES2, object);
+    bne(rd, CMPRES2, l);
   }
 
   void BranchSignedGreater(Register rd, Register rs, Label* l) {
-    slt(CMPRES, rs, rd);  // CMPRES = rd > rs ? 1 : 0.
-    bne(CMPRES, ZR, l);
+    slt(CMPRES2, rs, rd);  // CMPRES2 = rd > rs ? 1 : 0.
+    bne(CMPRES2, ZR, l);
   }
 
   void BranchSignedGreater(Register rd, int32_t value, Label* l) {
-    LoadImmediate(CMPRES, value);
-    BranchSignedGreater(rd, CMPRES, l);
+    ASSERT(rd != CMPRES2);
+    LoadImmediate(CMPRES2, value);
+    BranchSignedGreater(rd, CMPRES2, l);
   }
 
   void BranchUnsignedGreater(Register rd, Register rs, Label* l) {
-    sltu(CMPRES, rs, rd);
-    bne(CMPRES, ZR, l);
+    sltu(CMPRES2, rs, rd);
+    bne(CMPRES2, ZR, l);
   }
 
   void BranchUnsignedGreater(Register rd, int32_t value, Label* l) {
-    LoadImmediate(CMPRES, value);
-    BranchUnsignedGreater(rd, CMPRES, l);
+    ASSERT(rd != CMPRES2);
+    LoadImmediate(CMPRES2, value);
+    BranchUnsignedGreater(rd, CMPRES2, l);
   }
 
   void BranchSignedGreaterEqual(Register rd, Register rs, Label* l) {
-    slt(CMPRES, rd, rs);  // CMPRES = rd < rs ? 1 : 0.
-    beq(CMPRES, ZR, l);  // If CMPRES = 0, then rd >= rs.
+    slt(CMPRES2, rd, rs);  // CMPRES2 = rd < rs ? 1 : 0.
+    beq(CMPRES2, ZR, l);  // If CMPRES2 = 0, then rd >= rs.
   }
 
   void BranchSignedGreaterEqual(Register rd, int32_t value, Label* l) {
     if (Utils::IsInt(kImmBits, value)) {
-      slti(CMPRES, rd, Immediate(value));
-      beq(CMPRES, ZR, l);
+      slti(CMPRES2, rd, Immediate(value));
+      beq(CMPRES2, ZR, l);
     } else {
-      LoadImmediate(CMPRES, value);
-      BranchSignedGreaterEqual(rd, CMPRES, l);
+      ASSERT(rd != CMPRES2);
+      LoadImmediate(CMPRES2, value);
+      BranchSignedGreaterEqual(rd, CMPRES2, l);
     }
   }
 
   void BranchUnsignedGreaterEqual(Register rd, Register rs, Label* l) {
-    sltu(CMPRES, rd, rs);  // CMPRES = rd < rs ? 1 : 0.
-    beq(CMPRES, ZR, l);
+    sltu(CMPRES2, rd, rs);  // CMPRES2 = rd < rs ? 1 : 0.
+    beq(CMPRES2, ZR, l);
   }
 
   void BranchUnsignedGreaterEqual(Register rd, int32_t value, Label* l) {
     if (Utils::IsUint(kImmBits, value)) {
-      sltiu(CMPRES, rd, Immediate(value));
-      beq(CMPRES, ZR, l);
+      sltiu(CMPRES2, rd, Immediate(value));
+      beq(CMPRES2, ZR, l);
     } else {
-      LoadImmediate(CMPRES, value);
-      BranchUnsignedGreaterEqual(rd, CMPRES, l);
+      ASSERT(rd != CMPRES2);
+      LoadImmediate(CMPRES2, value);
+      BranchUnsignedGreaterEqual(rd, CMPRES2, l);
     }
   }
 
   void BranchSignedLess(Register rd, Register rs, Label* l) {
     BranchSignedGreater(rs, rd, l);
   }
 
   void BranchSignedLess(Register rd, int32_t value, Label* l) {
     if (Utils::IsInt(kImmBits, value)) {
-      slti(CMPRES, rd, Immediate(value));
-      bne(CMPRES, ZR, l);
+      slti(CMPRES2, rd, Immediate(value));
+      bne(CMPRES2, ZR, l);
     } else {
-      LoadImmediate(CMPRES, value);
-      BranchSignedGreater(CMPRES, rd, l);
+      ASSERT(rd != CMPRES2);
+      LoadImmediate(CMPRES2, value);
+      BranchSignedGreater(CMPRES2, rd, l);
     }
   }
 
   void BranchUnsignedLess(Register rd, Register rs, Label* l) {
     BranchUnsignedGreater(rs, rd, l);
   }
 
   void BranchUnsignedLess(Register rd, int32_t value, Label* l) {
     if (Utils::IsUint(kImmBits, value)) {
-      sltiu(CMPRES, rd, Immediate(value));
-      bne(CMPRES, ZR, l);
+      sltiu(CMPRES2, rd, Immediate(value));
+      bne(CMPRES2, ZR, l);
     } else {
-      LoadImmediate(CMPRES, value);
-      BranchUnsignedGreater(CMPRES, rd, l);
+      ASSERT(rd != CMPRES2);
+      LoadImmediate(CMPRES2, value);
+      BranchUnsignedGreater(CMPRES2, rd, l);
     }
   }
 
   void BranchSignedLessEqual(Register rd, Register rs, Label* l) {
     BranchSignedGreaterEqual(rs, rd, l);
   }
 
   void BranchSignedLessEqual(Register rd, int32_t value, Label* l) {
-    LoadImmediate(CMPRES, value);
-    BranchSignedGreaterEqual(CMPRES, rd, l);
+    ASSERT(rd != CMPRES2);
+    LoadImmediate(CMPRES2, value);
+    BranchSignedGreaterEqual(CMPRES2, rd, l);
   }
 
   void BranchUnsignedLessEqual(Register rd, Register rs, Label* l) {
     BranchUnsignedGreaterEqual(rs, rd, l);
   }
 
   void BranchUnsignedLessEqual(Register rd, int32_t value, Label* l) {
-    LoadImmediate(CMPRES, value);
-    BranchUnsignedGreaterEqual(CMPRES, rd, l);
+    ASSERT(rd != CMPRES2);
+    LoadImmediate(CMPRES2, value);
+    BranchUnsignedGreaterEqual(CMPRES2, rd, l);
   }
 
   void Push(Register rt) {
     addiu(SP, SP, Immediate(-kWordSize));
     sw(rt, Address(SP));
   }
 
   void Pop(Register rt) {
     lw(rt, Address(SP));
     addiu(SP, SP, Immediate(kWordSize));
@@ skipping 38 matching lines @@
     swc1(hi, Address(base, offset + kWordSize));
   }
 
   void LoadDFromOffset(DRegister reg, Register base, int32_t offset) {
     FRegister lo = static_cast<FRegister>(reg * 2);
     FRegister hi = static_cast<FRegister>(reg * 2 + 1);
     lwc1(lo, Address(base, offset));
     lwc1(hi, Address(base, offset + kWordSize));
   }
 
+  // dest gets the address of the following instruction. If preserve ra is true
+  // RA is preserved using CMPRES1 as a temporary.
+  void GetNextPC(Register dest, bool preserve_ra) {

[regis, 2013/07/26 22:30:38]

The caller does not see that CMPRES1 is trashed. It would be better to pass an
explicit register in case RA needs to be preserved and kNoRegister if it does
not need to be preserved. This would replace the bool parameter.

[zra, 2013/07/26 23:29:03]

Done.

+    if (preserve_ra) {
+      mov(CMPRES1, RA);
+    }
+    EmitRegImmType(REGIMM, R0, BGEZAL, 1);
+    mov(dest, RA);
+    if (preserve_ra) {
+      mov(RA, CMPRES1);
+    }
+  }
+
   void ReserveAlignedFrameSpace(intptr_t frame_space);
 
   // Create a frame for calling into runtime that preserves all volatile
   // registers.  Frame's SP is guaranteed to be correctly aligned and
   // frame_space bytes are reserved under it.
   void EnterCallRuntimeFrame(intptr_t frame_space);
   void LeaveCallRuntimeFrame();
 
   void LoadWordFromPoolOffset(Register rd, int32_t offset);
   void LoadObject(Register rd, const Object& object);
@@ skipping 133 matching lines @@
                     FRegister fd,
                     Cop1Function func) {
     Emit(opcode << kOpcodeShift |
          fmt << kFmtShift |
          ft << kFtShift |
          fs << kFsShift |
          fd << kFdShift |
          func << kCop1FnShift);
   }
 
-  void EmitBranch(Opcode b, Register rs, Register rt, Label* label) {
-    if (label->IsBound()) {
-      // Relative destination from an instruction after the branch.
-      const int32_t dest =
-          label->Position() - (buffer_.Size() + Instr::kInstrSize);
-      const uint16_t dest_off = EncodeBranchOffset(dest, 0);
-      EmitIType(b, rs, rt, dest_off);
-    } else {
-      const int position = buffer_.Size();
-      const uint16_t dest_off = EncodeBranchOffset(label->position_, 0);
-      EmitIType(b, rs, rt, dest_off);
-      label->LinkTo(position);
-    }
-  }
 
-  void EmitRegImmBranch(RtRegImm b, Register rs, Label* label) {
-    if (label->IsBound()) {
-      // Relative destination from an instruction after the branch.
-      const int32_t dest =
-          label->Position() - (buffer_.Size() + Instr::kInstrSize);
-      const uint16_t dest_off = EncodeBranchOffset(dest, 0);
-      EmitRegImmType(REGIMM, rs, b, dest_off);
-    } else {
-      const int position = buffer_.Size();
-      const uint16_t dest_off = EncodeBranchOffset(label->position_, 0);
-      EmitRegImmType(REGIMM, rs, b, dest_off);
-      label->LinkTo(position);
-    }
-  }
-
-  void EmitFpuBranch(bool kind, Label *label) {
-    const int32_t b16 = kind ? (1 << 16) : 0;  // Bit 16 set for branch on true.
-    if (label->IsBound()) {
-      // Relative destination from an instruction after the branch.
-      const int32_t dest =
-          label->Position() - (buffer_.Size() + Instr::kInstrSize);
-      const uint16_t dest_off = EncodeBranchOffset(dest, 0);
-      Emit(COP1 << kOpcodeShift |
-           COP1_BC << kCop1SubShift |
-           b16 |
-           dest_off);
-    } else {
-      const int position = buffer_.Size();
-      const uint16_t dest_off = EncodeBranchOffset(label->position_, 0);
-      Emit(COP1 << kOpcodeShift |
-           COP1_BC << kCop1SubShift |
-           b16 |
-           dest_off);
-      label->LinkTo(position);
-    }
-  }
-
-  static int32_t EncodeBranchOffset(int32_t offset, int32_t instr);
-  static int DecodeBranchOffset(int32_t instr);
+  void EmitFarJump(int32_t offset, bool link);
+  void EmitFarBranch(Opcode b, Register rs, Register rt, int32_t offset);
+  void EmitFarRegImmBranch(RtRegImm b, Register rs, int32_t offset);
+  void EmitFarFpuBranch(bool kind, int32_t offset);
+  void EmitBranch(Opcode b, Register rs, Register rt, Label* label);
+  void EmitRegImmBranch(RtRegImm b, Register rs, Label* label);
+  void EmitFpuBranch(bool kind, Label *label);
 
   void EmitBranchDelayNop() {
     Emit(Instr::kNopInstruction);  // Branch delay NOP.
     delay_slot_available_ = true;
   }
 
   void StoreIntoObjectFilter(Register object, Register value, Label* no_update);
 
   // Shorter filtering sequence that assumes that value is not a smi.
   void StoreIntoObjectFilterNoSmi(Register object,
                                   Register value,
                                   Label* no_update);
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_MIPS_H_