Implements far branch targets for MIPS.

runtime/vm/stub_code_mips.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_MIPS)
 
 #include "vm/assembler.h"
 #include "vm/code_generator.h"
 #include "vm/compiler.h"
@@ skipping 282 matching lines @@
   __ addu(T1, FP, T1);
   __ AddImmediate(T1, kParamEndSlotFromFp * kWordSize);
   // T1: address of first argument on stack.
   // T2: address of first argument in array.
 
   Label loop, loop_exit;
   __ blez(A1, &loop_exit);
   __ delay_slot()->addiu(T2, V0,
                          Immediate(Array::data_offset() - kHeapObjectTag));
   __ Bind(&loop);
-  __ lw(TMP, Address(T1));
+  __ lw(T3, Address(T1));
   __ addiu(A1, A1, Immediate(-Smi::RawValue(1)));
   __ addiu(T1, T1, Immediate(-kWordSize));
   __ addiu(T2, T2, Immediate(kWordSize));
   __ bgez(A1, &loop);
-  __ delay_slot()->sw(TMP, Address(T2, -kWordSize));
+  __ delay_slot()->sw(T3, Address(T2, -kWordSize));
   __ Bind(&loop_exit);
 }
 
 
 // Input parameters:
 //   S5: ic-data.
 //   S4: arguments descriptor array.
 // Note: The receiver object is the first argument to the function being
 //       called, the stub accesses the receiver from this location directly
 //       when trying to resolve the call.
@@ skipping 263 matching lines @@
     __ and_(T3, T3, TMP1);
     __ addu(T2, T3, V0);
 
     // Check if the allocation fits into the remaining space.
     // V0: potential new object start.
     // A0: array element type.
     // A1: array length as Smi.
     // T0: points to new space object.
     // T2: potential next object start.
     // T3: array size.
-    __ lw(TMP1, Address(T0, Scavenger::end_offset()));
-    __ BranchUnsignedGreaterEqual(T2, TMP1, &slow_case);
+    __ lw(CMPRES1, Address(T0, Scavenger::end_offset()));
+    __ BranchUnsignedGreaterEqual(T2, CMPRES1, &slow_case);
 
     // Successfully allocated the object(s), now update top to point to
     // next object start and initialize the object.
     // V0: potential new object start.
     // T2: potential next object start.
     // T0: Points to new space object.
     __ sw(T2, Address(T0, Scavenger::top_offset()));
     __ addiu(V0, V0, Immediate(kHeapObjectTag));
 
     // V0: new object start as a tagged pointer.
@@ skipping 342 matching lines @@
     __ LoadImmediate(T5, heap->TopAddress());
     __ lw(V0, Address(T5, 0));
     __ addu(T3, T2, V0);
 
     // Check if the allocation fits into the remaining space.
     // V0: potential new object.
     // T1: number of context variables.
     // T2: object size.
     // T3: potential next object start.
     __ LoadImmediate(TMP1, heap->EndAddress());
-    __ lw(TMP1, Address(TMP1, 0));
+    __ lw(CMPRES1, Address(TMP1, 0));
     if (FLAG_use_slow_path) {
       __ b(&slow_case);
     } else {
-      __ BranchUnsignedGreaterEqual(T3, TMP1, &slow_case);
+      __ BranchUnsignedGreaterEqual(T3, CMPRES1, &slow_case);
     }
 
     // Successfully allocated the object, now update top to point to
     // next object start and initialize the object.
     // V0: new object.
     // T1: number of context variables.
     // T2: object size.
     // T3: next object start.
     __ sw(T3, Address(T5, 0));
     __ addiu(V0, V0, Immediate(kHeapObjectTag));
@@ skipping 34 matching lines @@
     // V0: new object.
     // T1: number of context variables.
     Label loop, loop_exit;
     __ blez(T1, &loop_exit);
     // Setup the parent field.
     __ delay_slot()->sw(T7, FieldAddress(V0, Context::parent_offset()));
     __ AddImmediate(T3, V0, Context::variable_offset(0) - kHeapObjectTag);
     __ sll(T1, T1, 2);
     __ Bind(&loop);
     __ addiu(T1, T1, Immediate(-kWordSize));
-    __ addu(TMP1, T3, T1);
+    __ addu(T4, T3, T1);
     __ bgtz(T1, &loop);
-    __ delay_slot()->sw(T7, Address(TMP1));
+    __ delay_slot()->sw(T7, Address(T4));
     __ Bind(&loop_exit);
 
     // Done allocating and initializing the context.
     // V0: new object.
     __ Ret();
 
     __ Bind(&slow_case);
   }
   // Create a stub frame as we are pushing some objects on the stack before
   // calling into the runtime.
@@ skipping 126 matching lines @@
       __ delay_slot()->mov(T4, T3);
       __ AddImmediate(T3, type_args_size);
       __ Bind(&no_instantiator);
       // T4: potential new object end and, if T4 != T3, potential new
       // InstantiatedTypeArguments object start.
     }
     // Check if the allocation fits into the remaining space.
     // T2: potential new object start.
     // T3: potential next object start.
     __ LoadImmediate(TMP1, heap->EndAddress());
-    __ lw(TMP1, Address(TMP1));
+    __ lw(CMPRES1, Address(TMP1));
     if (FLAG_use_slow_path) {
       __ b(&slow_case);
     } else {
-      __ BranchUnsignedGreaterEqual(T3, TMP1, &slow_case);
+      __ BranchUnsignedGreaterEqual(T3, CMPRES1, &slow_case);
     }
 
     // Successfully allocated the object(s), now update top to point to
     // next object start and initialize the object.
     __ sw(T3, Address(T5));
 
     if (is_cls_parameterized) {
       // Initialize the type arguments field in the object.
       // T2: new object start.
       // T4: potential new object end and, if T4 != T3, potential new
@@ skipping 143 matching lines @@
     __ AddImmediate(T3, T2, closure_size);
     if (is_implicit_instance_closure) {
       __ mov(T4, T3);  // T4: new context address.
       __ AddImmediate(T3, context_size);
     }
     // Check if the allocation fits into the remaining space.
     // T2: potential new closure object.
     // T3: address of top of heap.
     // T4: potential new context object (only if is_implicit_closure).
     __ LoadImmediate(TMP1, heap->EndAddress());
-    __ lw(TMP1, Address(TMP1));
+    __ lw(CMPRES1, Address(TMP1));
     if (FLAG_use_slow_path) {
       __ b(&slow_case);
     } else {
-      __ BranchUnsignedGreaterEqual(T3, TMP1, &slow_case);
+      __ BranchUnsignedGreaterEqual(T3, CMPRES1, &slow_case);
     }
 
     // Successfully allocated the object, now update top to point to
     // next object start and initialize the object.
     __ sw(T3, Address(T5));
 
     // T2: new closure object.
     // T4: new context object (only if is_implicit_closure).
     // Set the tags.
     uword tags = 0;
@@ skipping 334 matching lines @@
   // and the arguments descriptor array.
   __ addiu(SP, SP, Immediate(num_slots * kWordSize));
   __ LeaveStubFrame();
   Label call_target_function;
   __ BranchNotEqual(T3, reinterpret_cast<int32_t>(Object::null()),
                     &call_target_function);
 
   // NoSuchMethod or closure.
   // Mark IC call that it may be a closure call that does not collect
   // type feedback.
-  __ LoadImmediate(TMP1, 1);
+  __ LoadImmediate(T6, 1);
   __ Branch(&StubCode::InstanceFunctionLookupLabel());
-  __ delay_slot()->sb(TMP1, FieldAddress(S5, ICData::is_closure_call_offset()));
+  __ delay_slot()->sb(T6, FieldAddress(S5, ICData::is_closure_call_offset()));
 
   __ Bind(&found);
   // T0: Pointer to an IC data check group.
   const intptr_t target_offset = ICData::TargetIndexFor(num_args) * kWordSize;
   const intptr_t count_offset = ICData::CountIndexFor(num_args) * kWordSize;
   __ lw(T3, Address(T0, target_offset));
   __ lw(T4, Address(T0, count_offset));
 
   __ AddImmediateDetectOverflow(T4, T4, Smi::RawValue(1), T5, T6);
 
   __ bgez(T5, &call_target_function);  // No overflow.
   __ delay_slot()->sw(T4, Address(T0, count_offset));
 
   __ LoadImmediate(T1, Smi::RawValue(Smi::kMaxValue));
   __ sw(T1, Address(T0, count_offset));
 
   __ Bind(&call_target_function);
   // T3: Target function.
   __ lw(T3, FieldAddress(T3, Function::code_offset()));
   __ lw(T3, FieldAddress(T3, Code::instructions_offset()));
   __ AddImmediate(T3, Instructions::HeaderSize() - kHeapObjectTag);
   __ jr(T3);
 
   // Instance in T3, return its class-id in T3 as Smi.
   __ Bind(&get_class_id_as_smi);
   Label not_smi;
   // Test if Smi -> load Smi class for comparison.
-  __ andi(TMP1, T3, Immediate(kSmiTagMask));
-  __ bne(TMP1, ZR, &not_smi);
+  __ andi(CMPRES1, T3, Immediate(kSmiTagMask));
+  __ bne(CMPRES1, ZR, &not_smi);
   __ jr(RA);
   __ delay_slot()->addiu(T3, ZR, Immediate(Smi::RawValue(kSmiCid)));
 
   __ Bind(&not_smi);
   __ LoadClassId(T3, T3);
   __ jr(RA);
   __ delay_slot()->SmiTag(T3);
 }
 
 
@@ skipping 114 matching lines @@
 
   __ LoadImmediate(T1, Smi::RawValue(Smi::kMaxValue));
   __ sw(T1, Address(T0, count_offset));
 
   __ Bind(&increment_done);
 
   Label target_is_compiled;
   // Get function and call it, if possible.
   __ lw(T3, Address(T0, target_offset));
   __ lw(T4, FieldAddress(T3, Function::code_offset()));
-  __ LoadImmediate(TMP, reinterpret_cast<intptr_t>(Object::null()));
-  __ bne(T4, TMP, &target_is_compiled);
+  __ LoadImmediate(CMPRES1, reinterpret_cast<intptr_t>(Object::null()));
+  __ bne(T4, CMPRES1, &target_is_compiled);
 
   __ EnterStubFrame();
   // Preserve target function and IC data object.
   // Two preserved registers, one argument (function) => 3 slots.
   __ addiu(SP, SP, Immediate(-3 * kWordSize));
   __ sw(S5, Address(SP, 2 * kWordSize));  // Preserve IC data.
   __ sw(T3, Address(SP, 1 * kWordSize));  // Preserve function.
   __ sw(T3, Address(SP, 0 * kWordSize));  // Function argument.
   __ CallRuntime(kCompileFunctionRuntimeEntry);
   __ lw(T3, Address(SP, 1 * kWordSize));  // Restore function.
@@ skipping 78 matching lines @@
   // Create a stub frame as we are pushing some objects on the stack before
   // calling into the runtime.
   __ TraceSimMsg("BreakpointDynamicStub");
   __ EnterStubFrame();
   __ Push(S5);
   __ CallRuntime(kBreakpointDynamicHandlerRuntimeEntry);
   __ Pop(S5);
   __ LeaveStubFrame();
 
   // Find out which dispatch stub to call.
-  __ lw(TMP1, FieldAddress(S5, ICData::num_args_tested_offset()));
+  __ lw(T1, FieldAddress(S5, ICData::num_args_tested_offset()));
 
   Label one_arg, two_args, three_args;
-  __ BranchEqual(TMP1, 1, &one_arg);
-  __ BranchEqual(TMP1, 2, &two_args);
-  __ BranchEqual(TMP1, 3, &three_args);
+  __ BranchEqual(T1, 1, &one_arg);
+  __ BranchEqual(T1, 2, &two_args);
+  __ BranchEqual(T1, 3, &three_args);
   __ Stop("Unsupported number of arguments tested.");
 
   __ Bind(&one_arg);
   __ Branch(&StubCode::OneArgCheckInlineCacheLabel());
   __ Bind(&two_args);
   __ Branch(&StubCode::TwoArgsCheckInlineCacheLabel());
   __ Bind(&three_args);
   __ Branch(&StubCode::ThreeArgsCheckInlineCacheLabel());
   __ break_(0);
 }
@@ skipping 141 matching lines @@
 // T0: ICData.
 // V0: result.
 // TODO(srdjan): Move to VM stubs once Boolean objects become VM objects.
 void StubCode::GenerateEqualityWithNullArgStub(Assembler* assembler) {
   __ TraceSimMsg("EqualityWithNullArgStub");
   __ Comment("EqualityWithNullArgStub");
   __ EnterStubFrame();
   static const intptr_t kNumArgsTested = 2;
 #if defined(DEBUG)
   { Label ok;
-    __ lw(TMP1, FieldAddress(T0, ICData::num_args_tested_offset()));
-    __ BranchEqual(TMP1, kNumArgsTested, &ok);
+    __ lw(CMPRES1, FieldAddress(T0, ICData::num_args_tested_offset()));
+    __ BranchEqual(CMPRES1, kNumArgsTested, &ok);
     __ Stop("Incorrect ICData for equality");
     __ Bind(&ok);
   }
 #endif  // DEBUG
   // Check IC data, update if needed.
   // T0: IC data object (preserved).
   __ lw(T6, FieldAddress(T0, ICData::ic_data_offset()));
   // T6: ic_data_array with check entries: classes and target functions.
   __ AddImmediate(T6, Array::data_offset() - kHeapObjectTag);
   // T6: points directly to the first ic data array element.
@@ skipping 176 matching lines @@
   __ CallRuntime(kBigintCompareRuntimeEntry);
   __ TraceSimMsg("IdenticalWithNumberCheckStub return");
   // Result in V0, 0 means equal.
   __ LeaveStubFrame();
   __ b(&done);
   __ delay_slot()->mov(CMPRES, V0);
 
   __ Bind(&reference_compare);
   __ subu(CMPRES, left, right);
   __ Bind(&done);
-  // A branch or test after this comparison will check CMPRES == TMP1.
-  __ mov(TMP1, ZR);
+  // A branch or test after this comparison will check CMPRES1 == CMPRES2.
+  __ mov(CMPRES2, ZR);
 }
 
 
 // Called only from unoptimized code. All relevant registers have been saved.
 // RA: return address.
 // SP + 4: left operand.
 // SP + 0: right operand.
 // Returns: CMPRES is zero if equal, non-zero otherwise.
 void StubCode::GenerateUnoptimizedIdenticalWithNumberCheckStub(
     Assembler* assembler) {
@@ skipping 46 matching lines @@
   __ lw(left, Address(SP, 1 * kWordSize));
   __ lw(temp2, Address(SP, 2 * kWordSize));
   __ lw(temp1, Address(SP, 3 * kWordSize));
   __ Ret();
   __ delay_slot()->addiu(SP, SP, Immediate(4 * kWordSize));
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_MIPS