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| 1 /* linux/drivers/media/video/samsung/tv20/tv_out_s5pv210.h |
| 2 * |
| 3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. |
| 4 * http://www.samsung.com/ |
| 5 * |
| 6 * S5PV210 - tv out header file for Samsung TVOut driver |
| 7 * |
| 8 * This program is free software; you can redistribute it and/or modify |
| 9 * it under the terms of the GNU General Public License version 2 as |
| 10 * published by the Free Software Foundation. |
| 11 */ |
| 12 |
| 13 /* #define CONFIG_TVOUT_RAW_DBG */ |
| 14 |
| 15 /* common */ |
| 16 |
| 17 #define HDMI_START_NUM 0x1000 |
| 18 |
| 19 #define bit_add_l(val, addr) writel(readl(addr) | val, addr) |
| 20 #define bit_add_s(val, addr) writes(reads(addr) | val, addr) |
| 21 #define bit_add_b(val, addr) writeb(readb(addr) | val, addr) |
| 22 #define bit_del_l(val, addr) writel(readl(addr) & ~val, addr) |
| 23 #define bit_del_s(val, addr) writes(reads(addr) & ~val, addr) |
| 24 #define bit_del_b(val, addr) writeb(readb(addr) & ~val, addr) |
| 25 |
| 26 enum s5p_tv_audio_codec_type { |
| 27 PCM = 1, AC3, MP3, WMA |
| 28 }; |
| 29 |
| 30 enum s5p_endian_type { |
| 31 TVOUT_LITTLE_ENDIAN_MODE = 0, |
| 32 TVOUT_BIG_ENDIAN_MODE = 1 |
| 33 }; |
| 34 |
| 35 enum s5p_tv_disp_mode { |
| 36 TVOUT_NTSC_M = 0, |
| 37 TVOUT_PAL_BDGHI, |
| 38 TVOUT_PAL_M, |
| 39 TVOUT_PAL_N, |
| 40 TVOUT_PAL_NC, |
| 41 TVOUT_PAL_60, |
| 42 TVOUT_NTSC_443, |
| 43 |
| 44 TVOUT_480P_60_16_9 = HDMI_START_NUM, |
| 45 TVOUT_480P_60_4_3, |
| 46 TVOUT_480P_59, |
| 47 |
| 48 TVOUT_576P_50_16_9, |
| 49 TVOUT_576P_50_4_3, |
| 50 |
| 51 TVOUT_720P_60, |
| 52 TVOUT_720P_50, |
| 53 TVOUT_720P_59, |
| 54 |
| 55 TVOUT_1080P_60, |
| 56 TVOUT_1080P_50, |
| 57 TVOUT_1080P_59, |
| 58 TVOUT_1080P_30, |
| 59 |
| 60 TVOUT_1080I_60, |
| 61 TVOUT_1080I_50, |
| 62 TVOUT_1080I_59, |
| 63 }; |
| 64 |
| 65 enum s5p_tv_o_mode { |
| 66 TVOUT_OUTPUT_COMPOSITE, |
| 67 TVOUT_OUTPUT_SVIDEO, |
| 68 TVOUT_OUTPUT_COMPONENT_YPBPR_INERLACED, |
| 69 TVOUT_OUTPUT_COMPONENT_YPBPR_PROGRESSIVE, |
| 70 TVOUT_OUTPUT_COMPONENT_RGB_PROGRESSIVE, |
| 71 TVOUT_OUTPUT_HDMI, |
| 72 TVOUT_OUTPUT_HDMI_RGB, |
| 73 TVOUT_OUTPUT_DVI |
| 74 }; |
| 75 |
| 76 enum s5p_tv_clk_err { |
| 77 S5P_TV_CLK_ERR_NO_ERROR = 0, |
| 78 S5P_TV_CLK_ERR_NOT_INIT_PARAMETERS_UNDER_RUNNING = 0x4000, |
| 79 S5P_TV_CLK_ERR_NOT_SET_PARAMETERS_UNDER_STOP, |
| 80 S5P_TV_CLK_ERR_INVALID_PARAM |
| 81 }; |
| 82 |
| 83 enum s5p_tv_vp_err { |
| 84 VPROC_NO_ERROR = 0, |
| 85 S5P_TV_VP_ERR_NOT_INIT_PARAMETERS_UNDER_RUNNING = 0x2000, |
| 86 S5P_TV_VP_ERR_NOT_SET_PARAMETERS_UNDER_STOP, |
| 87 S5P_TV_VP_ERR_BASE_ADDRESS_MUST_DOUBLE_WORD_ALIGN, |
| 88 S5P_TV_VP_ERR_NOT_UPDATE_FOR_ANOTHER_UPDATE, |
| 89 S5P_TV_VP_ERR_INVALID_PARAM |
| 90 }; |
| 91 |
| 92 enum s5p_tv_vmx_err { |
| 93 VMIXER_NO_ERROR = 0, |
| 94 S5P_TV_VMX_ERR_NOT_INIT_PARAMETERS_UNDER_RUNNING = 0x1000, |
| 95 S5P_TV_VMX_ERR_NOT_SET_PARAMETERS_UNDER_STOP, |
| 96 S5P_TV_VMX_ERR_BASE_ADDRESS_MUST_WORD_ALIGN, |
| 97 S5P_TV_VMX_ERR_INVALID_PARAM |
| 98 }; |
| 99 |
| 100 enum s5p_tv_vmx_color_fmt { |
| 101 VM_DIRECT_RGB565 = 4, |
| 102 VM_DIRECT_RGB1555 = 5, |
| 103 VM_DIRECT_RGB4444 = 6, |
| 104 VM_DIRECT_RGB8888 = 7 |
| 105 }; |
| 106 |
| 107 enum s5p_tv_sd_err { |
| 108 SDOUT_NO_ERROR = 0, |
| 109 S5P_TV_SD_ERR_NOT_INIT_PARAMETERS_UNDER_RUNNING = 0x3000, |
| 110 S5P_TV_SD_ERR_NOT_SET_PARAMETERS_UNDER_STOP, |
| 111 S5P_TV_SD_ERR_INVALID_PARAM |
| 112 }; |
| 113 |
| 114 /* order ch2 - ch1 - ch0 */ |
| 115 enum s5p_sd_order { |
| 116 S5P_TV_SD_O_ORDER_COMPONENT_RGB_PRYPB, |
| 117 S5P_TV_SD_O_ORDER_COMPONENT_RBG_PRPBY, |
| 118 S5P_TV_SD_O_ORDER_COMPONENT_BGR_PBYPR, |
| 119 S5P_TV_SD_O_ORDER_COMPONENT_BRG_PBPRY, |
| 120 S5P_TV_SD_O_ORDER_COMPONENT_GRB_YPRPB, |
| 121 S5P_TV_SD_O_ORDER_COMPONENT_GBR_YPBPR, |
| 122 S5P_TV_SD_O_ORDER_COMPOSITE_CVBS_Y_C, |
| 123 S5P_TV_SD_O_ORDER_COMPOSITE_CVBS_C_Y, |
| 124 S5P_TV_SD_O_ORDER_COMPOSITE_Y_C_CVBS, |
| 125 S5P_TV_SD_O_ORDER_COMPOSITE_Y_CVBS_C, |
| 126 S5P_TV_SD_O_ORDER_COMPOSITE_C_CVBS_Y, |
| 127 S5P_TV_SD_O_ORDER_COMPOSITE_C_Y_CVBS |
| 128 }; |
| 129 |
| 130 /* HDMI */ |
| 131 enum s5p_tv_hdmi_err { |
| 132 HDMI_NO_ERROR = 0, |
| 133 S5P_TV_HDMI_ERR_NOT_INIT_PARAMETERS_UNDER_RUNNING = 0x6000, |
| 134 S5P_TV_HDMI_ERR_NOT_SET_PARAMETERS_UNDER_STOP, |
| 135 S5P_TV_HDMI_ERR_INVALID_PARAM |
| 136 }; |
| 137 |
| 138 enum s5p_hdmi_transmit { |
| 139 HDMI_DO_NOT_TANS = 0, |
| 140 HDMI_TRANS_ONCE, |
| 141 HDMI_TRANS_EVERY_SYNC |
| 142 }; |
| 143 |
| 144 enum s5p_hdmi_audio_type { |
| 145 HDMI_AUDIO_NO, |
| 146 HDMI_AUDIO_PCM |
| 147 }; |
| 148 |
| 149 /* common */ |
| 150 enum s5p_tv_active_polarity { |
| 151 TVOUT_POL_ACTIVE_LOW, |
| 152 TVOUT_POL_ACTIVE_HIGH |
| 153 }; |
| 154 |
| 155 enum s5p_yuv_fmt_component{ |
| 156 TVOUT_YUV_Y, |
| 157 TVOUT_YUV_CB, |
| 158 TVOUT_YUV_CR |
| 159 }; |
| 160 |
| 161 enum s5p_tv_clk_mout_hpll { |
| 162 S5P_TV_CLK_MOUT_HPLL_27M, |
| 163 S5P_TV_CLK_MOUT_HPLL_FOUT_HPLL |
| 164 }; |
| 165 |
| 166 enum s5p_tv_clk_vmiexr_srcclk { |
| 167 TVOUT_CLK_VMIXER_SRCCLK_CLK27M, |
| 168 TVOUT_CLK_VMIXER_SRCCLK_VCLK_54, |
| 169 TVOUT_CLK_VMIXER_SRCCLK_MOUT_HPLL |
| 170 }; |
| 171 |
| 172 /* video processor */ |
| 173 enum s5p_vp_src_color { |
| 174 VPROC_SRC_COLOR_NV12 = 0, |
| 175 VPROC_SRC_COLOR_NV12IW = 1, |
| 176 VPROC_SRC_COLOR_TILE_NV12 = 2, |
| 177 VPROC_SRC_COLOR_TILE_NV12IW = 3 |
| 178 }; |
| 179 |
| 180 enum s5p_vp_pxl_rate { |
| 181 VPROC_PIXEL_PER_RATE_1_1 = 0, |
| 182 VPROC_PIXEL_PER_RATE_1_2 = 1, |
| 183 VPROC_PIXEL_PER_RATE_1_3 = 2, |
| 184 VPROC_PIXEL_PER_RATE_1_4 = 3 |
| 185 }; |
| 186 |
| 187 enum s5p_vp_sharpness_control { |
| 188 VPROC_SHARPNESS_NO = 0, |
| 189 VPROC_SHARPNESS_MIN = 1, |
| 190 VPROC_SHARPNESS_MOD = 2, |
| 191 VPROC_SHARPNESS_MAX = 3 |
| 192 }; |
| 193 |
| 194 enum s5p_vp_line_eq { |
| 195 VProc_LINE_EQ_0 = 0, |
| 196 VProc_LINE_EQ_1 = 1, |
| 197 VProc_LINE_EQ_2 = 2, |
| 198 VProc_LINE_EQ_3 = 3, |
| 199 VProc_LINE_EQ_4 = 4, |
| 200 VProc_LINE_EQ_5 = 5, |
| 201 VProc_LINE_EQ_6 = 6, |
| 202 VProc_LINE_EQ_7 = 7 |
| 203 }; |
| 204 |
| 205 enum s5p_vp_mem_mode { |
| 206 VPROC_LINEAR_MODE, |
| 207 VPROC_2D_TILE_MODE |
| 208 }; |
| 209 |
| 210 enum s5p_vp_chroma_expansion { |
| 211 VPROC_USING_C_TOP, |
| 212 VPROC_USING_C_TOP_BOTTOM |
| 213 }; |
| 214 |
| 215 enum s5p_vp_filed_id_toggle{ |
| 216 S5P_TV_VP_FILED_ID_TOGGLE_USER, |
| 217 S5P_TV_VP_FILED_ID_TOGGLE_VSYNC |
| 218 }; |
| 219 |
| 220 enum s5p_vp_field { |
| 221 VPROC_TOP_FIELD, |
| 222 VPROC_BOTTOM_FIELD |
| 223 }; |
| 224 |
| 225 enum s5p_vp_poly_coeff { |
| 226 VPROC_POLY8_Y0_LL = 0, |
| 227 VPROC_POLY8_Y0_LH, |
| 228 VPROC_POLY8_Y0_HL, |
| 229 VPROC_POLY8_Y0_HH, |
| 230 VPROC_POLY8_Y1_LL, |
| 231 VPROC_POLY8_Y1_LH, |
| 232 VPROC_POLY8_Y1_HL, |
| 233 VPROC_POLY8_Y1_HH, |
| 234 VPROC_POLY8_Y2_LL, |
| 235 VPROC_POLY8_Y2_LH, |
| 236 VPROC_POLY8_Y2_HL, |
| 237 VPROC_POLY8_Y2_HH, |
| 238 VPROC_POLY8_Y3_LL, |
| 239 VPROC_POLY8_Y3_LH, |
| 240 VPROC_POLY8_Y3_HL, |
| 241 VPROC_POLY8_Y3_HH, |
| 242 VPROC_POLY4_Y0_LL = 32, |
| 243 VPROC_POLY4_Y0_LH, |
| 244 VPROC_POLY4_Y0_HL, |
| 245 VPROC_POLY4_Y0_HH, |
| 246 VPROC_POLY4_Y1_LL, |
| 247 VPROC_POLY4_Y1_LH, |
| 248 VPROC_POLY4_Y1_HL, |
| 249 VPROC_POLY4_Y1_HH, |
| 250 VPROC_POLY4_Y2_LL, |
| 251 VPROC_POLY4_Y2_LH, |
| 252 VPROC_POLY4_Y2_HL, |
| 253 VPROC_POLY4_Y2_HH, |
| 254 VPROC_POLY4_Y3_LL, |
| 255 VPROC_POLY4_Y3_LH, |
| 256 VPROC_POLY4_Y3_HL, |
| 257 VPROC_POLY4_Y3_HH, |
| 258 VPROC_POLY4_C0_LL, |
| 259 VPROC_POLY4_C0_LH, |
| 260 VPROC_POLY4_C0_HL, |
| 261 VPROC_POLY4_C0_HH, |
| 262 VPROC_POLY4_C1_LL, |
| 263 VPROC_POLY4_C1_LH, |
| 264 VPROC_POLY4_C1_HL, |
| 265 VPROC_POLY4_C1_HH |
| 266 }; |
| 267 |
| 268 enum s5p_vp_csc_coeff { |
| 269 VPROC_CSC_Y2Y_COEF = 0, |
| 270 VPROC_CSC_CB2Y_COEF, |
| 271 VPROC_CSC_CR2Y_COEF, |
| 272 VPROC_CSC_Y2CB_COEF, |
| 273 VPROC_CSC_CB2CB_COEF, |
| 274 VPROC_CSC_CR2CB_COEF, |
| 275 VPROC_CSC_Y2CR_COEF, |
| 276 VPROC_CSC_CB2CR_COEF, |
| 277 VPROC_CSC_CR2CR_COEF |
| 278 }; |
| 279 |
| 280 enum s5p_vp_csc_type { |
| 281 VPROC_CSC_SD_HD, |
| 282 VPROC_CSC_HD_SD |
| 283 }; |
| 284 |
| 285 enum s5p_tv_vp_filter_h_pp { |
| 286 /* Don't change the order and the value */ |
| 287 VPROC_PP_H_NORMAL = 0, |
| 288 VPROC_PP_H_8_9, /* 720 to 640 */ |
| 289 VPROC_PP_H_1_2, |
| 290 VPROC_PP_H_1_3, |
| 291 VPROC_PP_H_1_4 |
| 292 }; |
| 293 |
| 294 enum s5p_tv_vp_filter_v_pp { |
| 295 /* Don't change the order and the value */ |
| 296 VPROC_PP_V_NORMAL = 0, |
| 297 VPROC_PP_V_5_6, /* PAL to NTSC */ |
| 298 VPROC_PP_V_3_4, |
| 299 VPROC_PP_V_1_2, |
| 300 VPROC_PP_V_1_3, |
| 301 VPROC_PP_V_1_4 |
| 302 }; |
| 303 |
| 304 /* video mixer */ |
| 305 enum s5p_vmx_burst_mode { |
| 306 VM_BURST_8 = 0, |
| 307 VM_BURST_16 = 1 |
| 308 }; |
| 309 |
| 310 enum s5p_tv_vmx_layer { |
| 311 VM_VIDEO_LAYER = 2, |
| 312 VM_GPR0_LAYER = 0, |
| 313 VM_GPR1_LAYER = 1 |
| 314 }; |
| 315 |
| 316 enum s5p_tv_vmx_bg_color_num { |
| 317 VMIXER_BG_COLOR_0 = 0, |
| 318 VMIXER_BG_COLOR_1 = 1, |
| 319 VMIXER_BG_COLOR_2 = 2 |
| 320 }; |
| 321 |
| 322 enum s5p_tv_coef_y_mode { |
| 323 VMIXER_COEF_Y_NARROW = 0, |
| 324 VMIXER_COEF_Y_WIDE = 1 |
| 325 }; |
| 326 |
| 327 enum s5p_tv_vmx_csc_type { |
| 328 VMIXER_CSC_RGB_TO_YUV601_LR, |
| 329 VMIXER_CSC_RGB_TO_YUV601_FR, |
| 330 VMIXER_CSC_RGB_TO_YUV709_LR, |
| 331 VMIXER_CSC_RGB_TO_YUV709_FR |
| 332 }; |
| 333 |
| 334 enum s5p_tv_vmx_rgb { |
| 335 RGB601_0_255, |
| 336 RGB601_16_235, |
| 337 RGB709_0_255, |
| 338 RGB709_16_235 |
| 339 }; |
| 340 |
| 341 enum s5p_tv_vmx_out_type{ |
| 342 MX_YUV444, |
| 343 MX_RGB888 |
| 344 }; |
| 345 |
| 346 /* TV encoder */ |
| 347 enum s5p_sd_level{ |
| 348 S5P_TV_SD_LEVEL_0IRE, |
| 349 S5P_TV_SD_LEVEL_75IRE |
| 350 }; |
| 351 |
| 352 enum s5p_sd_vsync_ratio{ |
| 353 SDOUT_VTOS_RATIO_10_4, |
| 354 SDOUT_VTOS_RATIO_7_3 |
| 355 }; |
| 356 |
| 357 enum s5p_sd_sync_sig_pin{ |
| 358 SDOUT_SYNC_SIG_NO, |
| 359 SDOUT_SYNC_SIG_YG, |
| 360 SDOUT_SYNC_SIG_ALL |
| 361 }; |
| 362 |
| 363 enum s5p_sd_closed_caption_type { |
| 364 SDOUT_NO_INS, |
| 365 SDOUT_INS_1, |
| 366 SDOUT_INS_2, |
| 367 SDOUT_INS_OTHERS |
| 368 }; |
| 369 |
| 370 enum s5p_sd_channel_sel { |
| 371 SDOUT_CHANNEL_0 = 0, |
| 372 SDOUT_CHANNEL_1 = 1, |
| 373 SDOUT_CHANNEL_2 = 2 |
| 374 }; |
| 375 |
| 376 enum s5p_sd_vesa_rgb_sync_type { |
| 377 SDOUT_VESA_RGB_SYNC_COMPOSITE, |
| 378 SDOUT_VESA_RGB_SYNC_SEPARATE |
| 379 }; |
| 380 |
| 381 enum s5p_sd_525_copy_permit { |
| 382 SDO_525_COPY_PERMIT, |
| 383 SDO_525_ONECOPY_PERMIT, |
| 384 SDO_525_NOCOPY_PERMIT |
| 385 }; |
| 386 |
| 387 enum s5p_sd_525_mv_psp { |
| 388 SDO_525_MV_PSP_OFF, |
| 389 SDO_525_MV_PSP_ON_2LINE_BURST, |
| 390 SDO_525_MV_PSP_ON_BURST_OFF, |
| 391 SDO_525_MV_PSP_ON_4LINE_BURST, |
| 392 }; |
| 393 |
| 394 enum s5p_sd_525_copy_info { |
| 395 SDO_525_COPY_INFO, |
| 396 SDO_525_DEFAULT, |
| 397 }; |
| 398 |
| 399 enum s5p_sd_525_aspect_ratio { |
| 400 SDO_525_4_3_NORMAL, |
| 401 SDO_525_16_9_ANAMORPIC, |
| 402 SDO_525_4_3_LETTERBOX |
| 403 }; |
| 404 |
| 405 enum s5p_sd_625_subtitles { |
| 406 SDO_625_NO_OPEN_SUBTITLES, |
| 407 SDO_625_INACT_OPEN_SUBTITLES, |
| 408 SDO_625_OUTACT_OPEN_SUBTITLES |
| 409 }; |
| 410 |
| 411 enum s5p_sd_625_camera_film{ |
| 412 SDO_625_CAMERA, |
| 413 SDO_625_FILM |
| 414 }; |
| 415 |
| 416 enum s5p_sd_625_color_encoding { |
| 417 SDO_625_NORMAL_PAL, |
| 418 SDO_625_MOTION_ADAPTIVE_COLORPLUS |
| 419 }; |
| 420 |
| 421 enum s5p_sd_625_aspect_ratio { |
| 422 SDO_625_4_3_FULL_576, |
| 423 SDO_625_14_9_LETTERBOX_CENTER_504, |
| 424 SDO_625_14_9_LETTERBOX_TOP_504, |
| 425 SDO_625_16_9_LETTERBOX_CENTER_430, |
| 426 SDO_625_16_9_LETTERBOX_TOP_430, |
| 427 SDO_625_16_9_LETTERBOX_CENTER, |
| 428 SDO_625_14_9_FULL_CENTER_576, |
| 429 SDO_625_16_9_ANAMORPIC_576 |
| 430 }; |
| 431 |
| 432 /* HDMI */ |
| 433 enum s5p_tv_hdmi_csc_type { |
| 434 HDMI_CSC_YUV601_TO_RGB_LR, |
| 435 HDMI_CSC_YUV601_TO_RGB_FR, |
| 436 HDMI_CSC_YUV709_TO_RGB_LR, |
| 437 HDMI_CSC_YUV709_TO_RGB_FR, |
| 438 HDMI_CSC_YUV601_TO_YUV709, |
| 439 HDMI_CSC_RGB_FR_TO_RGB_LR, |
| 440 HDMI_CSC_RGB_FR_TO_YUV601, |
| 441 HDMI_CSC_RGB_FR_TO_YUV709, |
| 442 HDMI_BYPASS |
| 443 }; |
| 444 |
| 445 /* |
| 446 * Color Depth for HDMI HW (settings and GCP packet), |
| 447 * EDID and PHY HW |
| 448 */ |
| 449 enum s5p_hdmi_color_depth { |
| 450 HDMI_CD_48, |
| 451 HDMI_CD_36, |
| 452 HDMI_CD_30, |
| 453 HDMI_CD_24 |
| 454 }; |
| 455 |
| 456 enum phy_freq { |
| 457 ePHY_FREQ_25_200, |
| 458 ePHY_FREQ_25_175, |
| 459 ePHY_FREQ_27, |
| 460 ePHY_FREQ_27_027, |
| 461 ePHY_FREQ_54, |
| 462 ePHY_FREQ_54_054, |
| 463 ePHY_FREQ_74_250, |
| 464 ePHY_FREQ_74_176, |
| 465 ePHY_FREQ_148_500, |
| 466 ePHY_FREQ_148_352, |
| 467 ePHY_FREQ_108_108, |
| 468 ePHY_FREQ_72, |
| 469 ePHY_FREQ_25, |
| 470 ePHY_FREQ_65, |
| 471 ePHY_FREQ_108, |
| 472 ePHY_FREQ_162 |
| 473 }; |
| 474 |
| 475 /* video format for HDMI HW (timings and AVI) and EDID */ |
| 476 enum s5p_hdmi_v_fmt { |
| 477 v640x480p_60Hz = 0, |
| 478 v720x480p_60Hz, |
| 479 v1280x720p_60Hz, |
| 480 v1920x1080i_60Hz, |
| 481 v720x480i_60Hz, |
| 482 v720x240p_60Hz, |
| 483 v2880x480i_60Hz, |
| 484 v2880x240p_60Hz, |
| 485 v1440x480p_60Hz, |
| 486 v1920x1080p_60Hz, |
| 487 v720x576p_50Hz, |
| 488 v1280x720p_50Hz, |
| 489 v1920x1080i_50Hz, |
| 490 v720x576i_50Hz, |
| 491 v720x288p_50Hz, |
| 492 v2880x576i_50Hz, |
| 493 v2880x288p_50Hz, |
| 494 v1440x576p_50Hz, |
| 495 v1920x1080p_50Hz, |
| 496 v1920x1080p_24Hz, |
| 497 v1920x1080p_25Hz, |
| 498 v1920x1080p_30Hz, |
| 499 v2880x480p_60Hz, |
| 500 v2880x576p_50Hz, |
| 501 v1920x1080i_50Hz_1250, |
| 502 v1920x1080i_100Hz, |
| 503 v1280x720p_100Hz, |
| 504 v720x576p_100Hz, |
| 505 v720x576i_100Hz, |
| 506 v1920x1080i_120Hz, |
| 507 v1280x720p_120Hz, |
| 508 v720x480p_120Hz, |
| 509 v720x480i_120Hz, |
| 510 v720x576p_200Hz, |
| 511 v720x576i_200Hz, |
| 512 v720x480p_240Hz, |
| 513 v720x480i_240Hz, |
| 514 v720x480p_59Hz, |
| 515 v1280x720p_59Hz, |
| 516 v1920x1080i_59Hz, |
| 517 v1920x1080p_59Hz, |
| 518 |
| 519 }; |
| 520 |
| 521 enum s5p_tv_hdmi_disp_mode { |
| 522 S5P_TV_HDMI_DISP_MODE_480P_60 = 0, |
| 523 S5P_TV_HDMI_DISP_MODE_576P_50 = 1, |
| 524 S5P_TV_HDMI_DISP_MODE_720P_60 = 2, |
| 525 S5P_TV_HDMI_DISP_MODE_720P_50 = 3, |
| 526 S5P_TV_HDMI_DISP_MODE_1080I_60 = 4, |
| 527 S5P_TV_HDMI_DISP_MODE_1080I_50 = 5, |
| 528 S5P_TV_HDMI_DISP_MODE_VGA_60 = 6, |
| 529 S5P_TV_HDMI_DISP_MODE_1080P_60 = 7, |
| 530 S5P_TV_HDMI_DISP_MODE_1080P_50 = 8, |
| 531 S5P_TV_HDMI_DISP_MODE_NUM = 9 |
| 532 }; |
| 533 |
| 534 /* pixel aspect ratio for HDMI HW (AVI packet and EDID) */ |
| 535 enum s5p_tv_hdmi_pxl_aspect { |
| 536 HDMI_PIXEL_RATIO_4_3, |
| 537 HDMI_PIXEL_RATIO_16_9 |
| 538 }; |
| 539 |
| 540 enum s5p_tv_hdmi_interrrupt { |
| 541 HDMI_IRQ_PIN_POLAR_CTL = 7, |
| 542 HDMI_IRQ_GLOBAL = 6, |
| 543 HDMI_IRQ_I2S = 5, |
| 544 HDMI_IRQ_CEC = 4, |
| 545 HDMI_IRQ_HPD_PLUG = 3, |
| 546 HDMI_IRQ_HPD_UNPLUG = 2, |
| 547 HDMI_IRQ_SPDIF = 1, |
| 548 HDMI_IRQ_HDCP = 0 |
| 549 }; |
| 550 |
| 551 typedef int (*hdmi_isr)(int irq); |
| 552 |
| 553 extern void __iomem *hdmi_base; |
| 554 |
| 555 extern wait_queue_head_t s5ptv_wq; |
| 556 |
| 557 /* must be checked */ |
| 558 extern u8 hdcp_protocol_status; |
| 559 /* 0 - hdcp stopped, 1 - hdcp started, 2 - hdcp reset */ |
| 560 |
| 561 extern int s5p_hdmi_register_isr(hdmi_isr isr, u8 irq_num); |
| 562 extern void s5p_hdmi_enable_interrupts(enum s5p_tv_hdmi_interrrupt intr); |
| 563 extern void s5p_hdmi_disable_interrupts(enum s5p_tv_hdmi_interrrupt intr); |
| 564 extern void s5p_hdmi_hpd_gen(void); |
| 565 |
| 566 extern bool tv_start_hdcp(void); |
| 567 extern bool tv_stop_hdcp(void); |
| 568 |
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