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1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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5716 opcode == BEQL || | 5716 opcode == BEQL || |
5717 opcode == BNEL || | 5717 opcode == BNEL || |
5718 opcode == BLEZL || | 5718 opcode == BLEZL || |
5719 opcode == BGTZL); | 5719 opcode == BGTZL); |
5720 opcode = (cond == eq) ? BEQ : BNE; | 5720 opcode = (cond == eq) ? BEQ : BNE; |
5721 instr = (instr & ~kOpcodeMask) | opcode; | 5721 instr = (instr & ~kOpcodeMask) | opcode; |
5722 masm_.emit(instr); | 5722 masm_.emit(instr); |
5723 } | 5723 } |
5724 | 5724 |
5725 | 5725 |
5726 void MacroAssembler::FlooringDiv(Register result, | 5726 void MacroAssembler::TruncatingDiv(Register result, |
5727 Register dividend, | 5727 Register dividend, |
5728 int32_t divisor) { | 5728 int32_t divisor) { |
5729 ASSERT(!dividend.is(result)); | 5729 ASSERT(!dividend.is(result)); |
5730 ASSERT(!dividend.is(at)); | 5730 ASSERT(!dividend.is(at)); |
5731 ASSERT(!result.is(at)); | 5731 ASSERT(!result.is(at)); |
5732 MultiplierAndShift ms(divisor); | 5732 MultiplierAndShift ms(divisor); |
5733 li(at, Operand(ms.multiplier())); | 5733 li(at, Operand(ms.multiplier())); |
5734 Mult(dividend, Operand(at)); | 5734 Mult(dividend, Operand(at)); |
5735 mfhi(result); | 5735 mfhi(result); |
5736 if (divisor > 0 && ms.multiplier() < 0) { | 5736 if (divisor > 0 && ms.multiplier() < 0) { |
5737 Addu(result, result, Operand(dividend)); | 5737 Addu(result, result, Operand(dividend)); |
5738 } | 5738 } |
5739 if (divisor < 0 && ms.multiplier() > 0) { | 5739 if (divisor < 0 && ms.multiplier() > 0) { |
5740 Subu(result, result, Operand(dividend)); | 5740 Subu(result, result, Operand(dividend)); |
5741 } | 5741 } |
5742 if (ms.shift() > 0) { | 5742 if (ms.shift() > 0) sra(result, result, ms.shift()); |
5743 sra(result, result, ms.shift()); | 5743 srl(at, dividend, 31); |
5744 } | 5744 Addu(result, result, Operand(at)); |
5745 } | 5745 } |
5746 | 5746 |
5747 | 5747 |
5748 } } // namespace v8::internal | 5748 } } // namespace v8::internal |
5749 | 5749 |
5750 #endif // V8_TARGET_ARCH_MIPS | 5750 #endif // V8_TARGET_ARCH_MIPS |
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