A64: Have the simulator fpcr_ members return appropriate types.

src/a64/simulator-a64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 598 matching lines @@
                                 int64_t src1,
                                 int64_t src2,
                                 int64_t carry_in) {
   ASSERT((carry_in == 0) || (carry_in == 1));
   ASSERT((reg_size == kXRegSizeInBits) || (reg_size == kWRegSizeInBits));
 
   uint64_t u1, u2;
   int64_t result;
   int64_t signed_sum = src1 + src2 + carry_in;
 
-  uint32_t N, Z, C, V;
+  bool N, Z, C, V;
 
   if (reg_size == kWRegSizeInBits) {
     u1 = static_cast<uint64_t>(src1) & kWRegMask;
     u2 = static_cast<uint64_t>(src2) & kWRegMask;
 
     result = signed_sum & kWRegMask;
     // Compute the C flag by comparing the sum to the max unsigned integer.
     C = ((kWMaxUInt - u1) < (u2 + carry_in)) ||
         ((kWMaxUInt - u1 - carry_in) < u2);
     // Overflow iff the sign bit is the same for the two inputs and different
@@ skipping 194 matching lines @@
   // TODO(jbramley): Find a more elegant way of defining these.
   char const * const clr_normal     = (FLAG_log_colour) ? ("\033[m") : ("");
   char const * const clr_flag_name  = (FLAG_log_colour) ? ("\033[1;30m") : ("");
   char const * const clr_flag_value = (FLAG_log_colour) ? ("\033[1;37m") : ("");
 
   static SimSystemRegister last_nzcv;
   if (print_all || first_run || (last_nzcv.RawValue() != nzcv().RawValue())) {
     fprintf(stream_, "# %sFLAGS: %sN:%d Z:%d C:%d V:%d%s\n",
             clr_flag_name,
             clr_flag_value,
-            N(), Z(), C(), V(),
+            nzcv().N(), nzcv().Z(), nzcv().C(), nzcv().V(),
             clr_normal);
   }
   last_nzcv = nzcv();
 
   static SimSystemRegister last_fpcr;
   if (print_all || first_run || (last_fpcr.RawValue() != fpcr().RawValue())) {
     static const char * rmode[] = {
       "0b00 (Round to Nearest)",
       "0b01 (Round towards Plus Infinity)",
       "0b10 (Round towards Minus Infinity)",
@@ skipping 283 matching lines @@
   int64_t new_val;
 
   if ((instr->Mask(AddSubOpMask) == SUB) || instr->Mask(AddSubOpMask) == SUBS) {
     op2 = ~op2;
   }
 
   new_val = AddWithCarry(reg_size,
                          instr->FlagsUpdate(),
                          reg(reg_size, instr->Rn()),
                          op2,
-                         C());
+                         nzcv().C());
 
   set_reg(reg_size, instr->Rd(), new_val);
 }
 
 
 void Simulator::VisitLogicalShifted(Instruction* instr) {
   unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits
                                              : kWRegSizeInBits;
   Shift shift_type = static_cast<Shift>(instr->ShiftDP());
   unsigned shift_amount = instr->ImmDPShift();
@@ skipping 775 matching lines @@
   }
 }
 
 
 void Simulator::VisitFPIntegerConvert(Instruction* instr) {
   AssertSupportedFPCR();
 
   unsigned dst = instr->Rd();
   unsigned src = instr->Rn();
 
-  FPRounding round = RMode();
+  FPRounding round = fpcr().RMode();
 
   switch (instr->Mask(FPIntegerConvertMask)) {
     case FCVTAS_ws: set_wreg(dst, FPToInt32(sreg(src), FPTieAway)); break;
     case FCVTAS_xs: set_xreg(dst, FPToInt64(sreg(src), FPTieAway)); break;
     case FCVTAS_wd: set_wreg(dst, FPToInt32(dreg(src), FPTieAway)); break;
     case FCVTAS_xd: set_xreg(dst, FPToInt64(dreg(src), FPTieAway)); break;
     case FCVTAU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPTieAway)); break;
     case FCVTAU_xs: set_xreg(dst, FPToUInt64(sreg(src), FPTieAway)); break;
     case FCVTAU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPTieAway)); break;
     case FCVTAU_xd: set_xreg(dst, FPToUInt64(dreg(src), FPTieAway)); break;
@@ skipping 64 matching lines @@
 }
 
 
 void Simulator::VisitFPFixedPointConvert(Instruction* instr) {
   AssertSupportedFPCR();
 
   unsigned dst = instr->Rd();
   unsigned src = instr->Rn();
   int fbits = 64 - instr->FPScale();
 
-  FPRounding round = RMode();
+  FPRounding round = fpcr().RMode();
 
   switch (instr->Mask(FPFixedPointConvertMask)) {
     // A 32-bit input can be handled in the same way as a 64-bit input, since
     // the sign- or zero-extension will not affect the conversion.
     case SCVTF_dx_fixed:
       set_dreg(dst, FixedToDouble(xreg(src), fbits, round));
       break;
     case SCVTF_dw_fixed:
       set_dreg(dst, FixedToDouble(wreg(src), fbits, round));
       break;
@@ skipping 439 matching lines @@
     }
     default: UNIMPLEMENTED();
   }
   return int_result;
 }
 
 
 double Simulator::FPToDouble(float value) {
   switch (std::fpclassify(value)) {
     case FP_NAN: {
-      if (DN()) return kFP64DefaultNaN;
+      if (fpcr().DN()) return kFP64DefaultNaN;
 
       // Convert NaNs as the processor would:
       //  - The sign is propagated.
       //  - The payload (mantissa) is transferred entirely, except that the top
       //    bit is forced to '1', making the result a quiet NaN. The unused
       //    (low-order) payload bits are set to 0.
       uint32_t raw = float_to_rawbits(value);
 
       uint64_t sign = raw >> 31;
       uint64_t exponent = (1 << 11) - 1;
@@ skipping 20 matching lines @@
 }
 
 
 float Simulator::FPToFloat(double value, FPRounding round_mode) {
   // Only the FPTieEven rounding mode is implemented.
   ASSERT(round_mode == FPTieEven);
   USE(round_mode);
 
   switch (std::fpclassify(value)) {
     case FP_NAN: {
-      if (DN()) return kFP32DefaultNaN;
+      if (fpcr().DN()) return kFP32DefaultNaN;
 
       // Convert NaNs as the processor would:
       //  - The sign is propagated.
       //  - The payload (mantissa) is transferred as much as possible, except
       //    that the top bit is forced to '1', making the result a quiet NaN.
       uint64_t raw = double_to_rawbits(value);
 
       uint32_t sign = raw >> 63;
       uint32_t exponent = (1 << 8) - 1;
       uint32_t payload = unsigned_bitextract_64(50, 52 - 23, raw);
@@ skipping 276 matching lines @@
   } else {
     // Other cases should be handled by standard arithmetic.
     return op1 - op2;
   }
 }
 
 
 template <typename T>
 T Simulator::FPProcessNaN(T op) {
   ASSERT(std::isnan(op));
-  return DN() ? FPDefaultNaN<T>() : ToQuietNaN(op);
+  return fpcr().DN() ? FPDefaultNaN<T>() : ToQuietNaN(op);
 }
 
 
 template <typename T>
 T Simulator::FPProcessNaNs(T op1, T op2) {
   if (IsSignallingNaN(op1)) {
     return FPProcessNaN(op1);
   } else if (IsSignallingNaN(op2)) {
     return FPProcessNaN(op2);
   } else if (std::isnan(op1)) {
@@ skipping 827 matching lines @@
     default:
       UNIMPLEMENTED();
   }
 }
 
 #endif  // USE_SIMULATOR
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_A64