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1 // Copyright 2013 the V8 project authors. All rights reserved. | 1 // Copyright 2013 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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218 V_(ImmSystemRegister, 19, 5, Bits) \ | 218 V_(ImmSystemRegister, 19, 5, Bits) \ |
219 V_(SysO0, 19, 19, Bits) \ | 219 V_(SysO0, 19, 19, Bits) \ |
220 V_(SysOp1, 18, 16, Bits) \ | 220 V_(SysOp1, 18, 16, Bits) \ |
221 V_(SysOp2, 7, 5, Bits) \ | 221 V_(SysOp2, 7, 5, Bits) \ |
222 V_(CRn, 15, 12, Bits) \ | 222 V_(CRn, 15, 12, Bits) \ |
223 V_(CRm, 11, 8, Bits) \ | 223 V_(CRm, 11, 8, Bits) \ |
224 | 224 |
225 | 225 |
226 #define SYSTEM_REGISTER_FIELDS_LIST(V_, M_) \ | 226 #define SYSTEM_REGISTER_FIELDS_LIST(V_, M_) \ |
227 /* NZCV */ \ | 227 /* NZCV */ \ |
228 V_(Flags, 31, 28, Bits) \ | 228 V_(Flags, 31, 28, Bits, uint32_t) \ |
229 V_(N, 31, 31, Bits) \ | 229 V_(N, 31, 31, Bits, bool) \ |
230 V_(Z, 30, 30, Bits) \ | 230 V_(Z, 30, 30, Bits, bool) \ |
231 V_(C, 29, 29, Bits) \ | 231 V_(C, 29, 29, Bits, bool) \ |
232 V_(V, 28, 28, Bits) \ | 232 V_(V, 28, 28, Bits, uint32_t) \ |
233 M_(NZCV, Flags_mask) \ | 233 M_(NZCV, Flags_mask) \ |
234 \ | 234 \ |
235 /* FPCR */ \ | 235 /* FPCR */ \ |
236 V_(AHP, 26, 26, Bits) \ | 236 V_(AHP, 26, 26, Bits, bool) \ |
237 V_(DN, 25, 25, Bits) \ | 237 V_(DN, 25, 25, Bits, bool) \ |
238 V_(FZ, 24, 24, Bits) \ | 238 V_(FZ, 24, 24, Bits, bool) \ |
239 V_(RMode, 23, 22, Bits) \ | 239 V_(RMode, 23, 22, Bits, FPRounding) \ |
240 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask) | 240 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask) |
241 | 241 |
242 | 242 |
243 // Fields offsets. | 243 // Fields offsets. |
244 #define DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, X) \ | 244 #define DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, unused_1, unused_2) \ |
245 const int Name##_offset = LowBit; \ | 245 const int Name##_offset = LowBit; \ |
246 const int Name##_width = HighBit - LowBit + 1; \ | 246 const int Name##_width = HighBit - LowBit + 1; \ |
247 const uint32_t Name##_mask = ((1 << Name##_width) - 1) << LowBit; | 247 const uint32_t Name##_mask = ((1 << Name##_width) - 1) << LowBit; |
| 248 #define DECLARE_INSTRUCTION_FIELDS_OFFSETS(Name, HighBit, LowBit, unused_1) \ |
| 249 DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, unused_1, unused_2) |
248 #define NOTHING(A, B) | 250 #define NOTHING(A, B) |
249 INSTRUCTION_FIELDS_LIST(DECLARE_FIELDS_OFFSETS) | 251 INSTRUCTION_FIELDS_LIST(DECLARE_INSTRUCTION_FIELDS_OFFSETS) |
250 SYSTEM_REGISTER_FIELDS_LIST(DECLARE_FIELDS_OFFSETS, NOTHING) | 252 SYSTEM_REGISTER_FIELDS_LIST(DECLARE_FIELDS_OFFSETS, NOTHING) |
251 #undef NOTHING | 253 #undef NOTHING |
252 #undef DECLARE_FIELDS_BITS | 254 #undef DECLARE_FIELDS_OFFSETS |
| 255 #undef DECLARE_INSTRUCTION_FIELDS_OFFSETS |
253 | 256 |
254 // ImmPCRel is a compound field (not present in INSTRUCTION_FIELDS_LIST), formed | 257 // ImmPCRel is a compound field (not present in INSTRUCTION_FIELDS_LIST), formed |
255 // from ImmPCRelLo and ImmPCRelHi. | 258 // from ImmPCRelLo and ImmPCRelHi. |
256 const int ImmPCRel_mask = ImmPCRelLo_mask | ImmPCRelHi_mask; | 259 const int ImmPCRel_mask = ImmPCRelLo_mask | ImmPCRelHi_mask; |
257 | 260 |
258 // Condition codes. | 261 // Condition codes. |
259 enum Condition { | 262 enum Condition { |
260 eq = 0, | 263 eq = 0, |
261 ne = 1, | 264 ne = 1, |
262 hs = 2, | 265 hs = 2, |
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1259 }; | 1262 }; |
1260 | 1263 |
1261 enum UnallocatedOp { | 1264 enum UnallocatedOp { |
1262 UnallocatedFixed = 0x00000000, | 1265 UnallocatedFixed = 0x00000000, |
1263 UnallocatedFMask = 0x00000000 | 1266 UnallocatedFMask = 0x00000000 |
1264 }; | 1267 }; |
1265 | 1268 |
1266 } } // namespace v8::internal | 1269 } } // namespace v8::internal |
1267 | 1270 |
1268 #endif // V8_A64_CONSTANTS_A64_H_ | 1271 #endif // V8_A64_CONSTANTS_A64_H_ |
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