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Issue 2027773002: Subzero, MIPS32: Handling floating point instructions fadd, fsub, fmul, fdiv (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Rebase for applying prerequisites Created 4 years, 6 months ago
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1 //===- subzero/src/IceInstMIPS32.def - X-Macros for MIPS insts --*- C++ -*-===// 1 //===- subzero/src/IceInstMIPS32.def - X-Macros for MIPS insts --*- C++ -*-===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file defines properties of MIPS32 instructions in the form of x-macros. 10 // This file defines properties of MIPS32 instructions in the form of x-macros.
(...skipping 83 matching lines...) Expand 10 before | Expand all | Expand 10 after
94 X(Reg_K0, 26, "k0", 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 94 X(Reg_K0, 26, "k0", 0, 0, 0, 0, 0, 0, 0, 0, 0, \
95 ALIASES1(Reg_K0)) \ 95 ALIASES1(Reg_K0)) \
96 X(Reg_K1, 27, "k1", 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 96 X(Reg_K1, 27, "k1", 0, 0, 0, 0, 0, 0, 0, 0, 0, \
97 ALIASES1(Reg_K1)) \ 97 ALIASES1(Reg_K1)) \
98 X(Reg_GP, 28, "gp", 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 98 X(Reg_GP, 28, "gp", 0, 0, 0, 0, 0, 0, 0, 0, 0, \
99 ALIASES1(Reg_GP)) \ 99 ALIASES1(Reg_GP)) \
100 X(Reg_SP, 29, "sp", 0, 0, 1, 0, 0, 0, 0, 0, 0, \ 100 X(Reg_SP, 29, "sp", 0, 0, 1, 0, 0, 0, 0, 0, 0, \
101 ALIASES1(Reg_SP)) \ 101 ALIASES1(Reg_SP)) \
102 X(Reg_FP, 30, "fp", 0, 0, 0, 1, 0, 0, 0, 0, 0, \ 102 X(Reg_FP, 30, "fp", 0, 0, 0, 1, 0, 0, 0, 0, 0, \
103 ALIASES1(Reg_FP)) \ 103 ALIASES1(Reg_FP)) \
104 X(Reg_RA, 31, "ra", 0, 1, 0, 0, 0, 0, 0, 0, 0, \ 104 X(Reg_RA, 31, "ra", 0, 0, 0, 0, 0, 0, 0, 0, 0, \
105 ALIASES1(Reg_RA)) \ 105 ALIASES1(Reg_RA)) \
106 X(Reg_LO, 0, "lo", 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 106 X(Reg_LO, 0, "lo", 0, 0, 0, 0, 0, 0, 0, 0, 0, \
107 ALIASES2(Reg_LO, Reg_LOHI)) \ 107 ALIASES2(Reg_LO, Reg_LOHI)) \
108 X(Reg_HI, 0, "hi", 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 108 X(Reg_HI, 0, "hi", 0, 0, 0, 0, 0, 0, 0, 0, 0, \
109 ALIASES2(Reg_HI, Reg_LOHI)) 109 ALIASES2(Reg_HI, Reg_LOHI))
110 110
111 #define REGMIPS32_FPR_TABLE \ 111 #define REGMIPS32_FPR_TABLE \
112 /* val, encode, name, scratch, preserved, stackptr, frameptr, \ 112 /* val, encode, name, scratch, preserved, stackptr, frameptr, \
113 isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \ 113 isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \
114 X(Reg_F0, 0, "f0", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F0)) \ 114 X(Reg_F0, 0, "f0", 0,0,0,0, 0,0,1,0,0, \
115 X(Reg_F1, 1, "f1", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F1)) \ 115 ALIASES2(Reg_F0, Reg_F0F1)) \
116 X(Reg_F2, 2, "f2", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F2)) \ 116 X(Reg_F1, 1, "f1", 0,0,0,0, 0,0,1,0,0, \
117 X(Reg_F3, 3, "f3", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F3)) \ 117 ALIASES2(Reg_F1, Reg_F0F1)) \
118 X(Reg_F4, 4, "f4", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F4)) \ 118 X(Reg_F2, 2, "f2", 0,0,0,0, 0,0,1,0,0, \
119 X(Reg_F5, 5, "f5", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F5)) \ 119 ALIASES2(Reg_F2, Reg_F2F3)) \
120 X(Reg_F6, 6, "f6", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F6)) \ 120 X(Reg_F3, 3, "f3", 0,0,0,0, 0,0,1,0,0, \
121 X(Reg_F7, 7, "f7", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F7)) \ 121 ALIASES2(Reg_F3, Reg_F2F3)) \
122 X(Reg_F8, 8, "f8", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F8)) \ 122 X(Reg_F4, 4, "f4", 1,0,0,0, 0,0,1,0,0, \
123 X(Reg_F9, 9, "f9", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F9)) \ 123 ALIASES2(Reg_F4, Reg_F4F5)) \
124 X(Reg_F10, 10, "f10", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F10)) \ 124 X(Reg_F5, 5, "f5", 1,0,0,0, 0,0,1,0,0, \
125 X(Reg_F11, 11, "f11", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F11)) \ 125 ALIASES2(Reg_F5, Reg_F4F5)) \
126 X(Reg_F12, 12, "f12", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F12)) \ 126 X(Reg_F6, 6, "f6", 1,0,0,0, 0,0,1,0,0, \
127 X(Reg_F13, 13, "f13", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F13)) \ 127 ALIASES2(Reg_F6, Reg_F6F7)) \
128 X(Reg_F14, 14, "f14", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F14)) \ 128 X(Reg_F7, 7, "f7", 1,0,0,0, 0,0,1,0,0, \
129 X(Reg_F15, 15, "f15", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F15)) \ 129 ALIASES2(Reg_F7, Reg_F6F7)) \
130 X(Reg_F16, 16, "f16", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F16)) \ 130 X(Reg_F8, 8, "f8", 1,0,0,0, 0,0,1,0,0, \
131 X(Reg_F17, 17, "f17", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F17)) \ 131 ALIASES2(Reg_F8, Reg_F8F9)) \
132 X(Reg_F18, 18, "f18", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F18)) \ 132 X(Reg_F9, 9, "f9", 1,0,0,0, 0,0,1,0,0, \
133 X(Reg_F19, 19, "f19", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F19)) \ 133 ALIASES2(Reg_F9, Reg_F8F9)) \
134 X(Reg_F20, 20, "f20", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F20)) \ 134 X(Reg_F10, 10, "f10", 1,0,0,0, 0,0,1,0,0, \
135 X(Reg_F21, 21, "f21", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F21)) \ 135 ALIASES2(Reg_F10, Reg_F10F11)) \
136 X(Reg_F22, 22, "f22", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F22)) \ 136 X(Reg_F11, 11, "f11", 1,0,0,0, 0,0,1,0,0, \
137 X(Reg_F23, 23, "f23", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F23)) \ 137 ALIASES2(Reg_F11, Reg_F10F11)) \
138 X(Reg_F24, 24, "f24", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F24)) \ 138 X(Reg_F12, 12, "f12", 0,0,0,0, 0,0,1,0,0, \
139 X(Reg_F25, 25, "f25", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F25)) \ 139 ALIASES2(Reg_F12, Reg_F12F13)) \
140 X(Reg_F26, 26, "f26", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F26)) \ 140 X(Reg_F13, 13, "f13", 0,0,0,0, 0,0,1,0,0, \
141 X(Reg_F27, 27, "f27", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F27)) \ 141 ALIASES2(Reg_F13, Reg_F12F13)) \
142 X(Reg_F28, 28, "f28", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F28)) \ 142 X(Reg_F14, 14, "f14", 0,0,0,0, 0,0,1,0,0, \
143 X(Reg_F29, 29, "f29", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F29)) \ 143 ALIASES2(Reg_F14, Reg_F14F15)) \
144 X(Reg_F30, 30, "f30", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F30)) \ 144 X(Reg_F15, 15, "f15", 0,0,0,0, 0,0,1,0,0, \
145 X(Reg_F31, 31, "f31", 1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F31)) 145 ALIASES2(Reg_F15, Reg_F14F15)) \
146 X(Reg_F16, 16, "f16", 1,0,0,0, 0,0,1,0,0, \
147 ALIASES2(Reg_F16, Reg_F16F17)) \
148 X(Reg_F17, 17, "f17", 1,0,0,0, 0,0,1,0,0, \
149 ALIASES2(Reg_F17, Reg_F16F17)) \
150 X(Reg_F18, 18, "f18", 1,0,0,0, 0,0,1,0,0, \
151 ALIASES2(Reg_F18, Reg_F18F19)) \
152 X(Reg_F19, 19, "f19", 1,0,0,0, 0,0,1,0,0, \
153 ALIASES2(Reg_F19, Reg_F18F19)) \
154 X(Reg_F20, 20, "f20", 0,1,0,0, 0,0,1,0,0, \
155 ALIASES2(Reg_F20, Reg_F20F21)) \
156 X(Reg_F21, 21, "f21", 0,1,0,0, 0,0,1,0,0, \
157 ALIASES2(Reg_F21, Reg_F20F21)) \
158 X(Reg_F22, 22, "f22", 0,1,0,0, 0,0,1,0,0, \
159 ALIASES2(Reg_F22, Reg_F22F23)) \
160 X(Reg_F23, 23, "f23", 0,1,0,0, 0,0,1,0,0, \
161 ALIASES2(Reg_F23, Reg_F22F23)) \
162 X(Reg_F24, 24, "f24", 0,1,0,0, 0,0,1,0,0, \
163 ALIASES2(Reg_F24, Reg_F24F25)) \
164 X(Reg_F25, 25, "f25", 0,1,0,0, 0,0,1,0,0, \
165 ALIASES2(Reg_F25, Reg_F24F25)) \
166 X(Reg_F26, 26, "f26", 0,1,0,0, 0,0,1,0,0, \
167 ALIASES2(Reg_F26, Reg_F26F27)) \
168 X(Reg_F27, 27, "f27", 0,1,0,0, 0,0,1,0,0, \
169 ALIASES2(Reg_F27, Reg_F26F27)) \
170 X(Reg_F28, 28, "f28", 0,1,0,0, 0,0,1,0,0, \
171 ALIASES2(Reg_F28, Reg_F28F29)) \
172 X(Reg_F29, 29, "f29", 0,1,0,0, 0,0,1,0,0, \
173 ALIASES2(Reg_F29, Reg_F28F29)) \
174 X(Reg_F30, 30, "f30", 0,1,0,0, 0,0,1,0,0, \
175 ALIASES2(Reg_F30, Reg_F30F31)) \
176 X(Reg_F31, 31, "f31", 0,1,0,0, 0,0,1,0,0, \
177 ALIASES2(Reg_F31, Reg_F30F31))
146 178
147 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr, 179 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
148 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) 180 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
149 // The following defines a table with the available pairs of consecutive i32 181 // The following defines a table with the available pairs of consecutive i32
150 // GPRs starting at an even GPR that is not r14. Those are used to hold i64 182 // GPRs starting at an even GPR that is not r14. Those are used to hold i64
151 // variables for atomic memory operations. If one of the registers in the pair 183 // variables for atomic memory operations. If one of the registers in the pair
152 // is preserved, then we mark the whole pair as preserved to help the register 184 // is preserved, then we mark the whole pair as preserved to help the register
153 // allocator. 185 // allocator.
154 #define REGMIPS32_I64PAIR_TABLE \ 186 #define REGMIPS32_I64PAIR_TABLE \
155 /* val, encode, name, scratch, preserved, stackptr, frameptr, \ 187 /* val, encode, name, scratch, preserved, stackptr, frameptr, \
(...skipping 23 matching lines...) Expand all
179 X(Reg_T8T9, 26, "t8, t9", 1, 0, 0, 0, 0, 1, 0, 0, 0, \ 211 X(Reg_T8T9, 26, "t8, t9", 1, 0, 0, 0, 0, 1, 0, 0, 0, \
180 ALIASES3(Reg_T8, Reg_T9, Reg_T8T9)) \ 212 ALIASES3(Reg_T8, Reg_T9, Reg_T8T9)) \
181 X(Reg_LOHI, 0, "lo, hi", 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 213 X(Reg_LOHI, 0, "lo, hi", 0, 0, 0, 0, 0, 0, 0, 0, 0, \
182 ALIASES3(Reg_LO, Reg_HI, Reg_LOHI)) \ 214 ALIASES3(Reg_LO, Reg_HI, Reg_LOHI)) \
183 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr, 215 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
184 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) 216 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
185 217
186 #define REGMIPS32_F64PAIR_TABLE \ 218 #define REGMIPS32_F64PAIR_TABLE \
187 /* val, encode, name, scratch, preserved, stackptr, frameptr, \ 219 /* val, encode, name, scratch, preserved, stackptr, frameptr, \
188 isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \ 220 isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \
189 X(Reg_F0F1, 0, "f0, f1", 1,0,0,0, 0,0,0,1,0, \ 221 X(Reg_F0F1, 0, "f0", 1,0,0,0, 0,0,0,1,0, \
190 ALIASES3(Reg_F0, Reg_F1, Reg_F0F1)) \ 222 ALIASES3(Reg_F0, Reg_F1, Reg_F0F1)) \
191 X(Reg_F2F3, 2, "f2, f3", 1,0,0,0, 0,0,0,1,0, \ 223 X(Reg_F2F3, 2, "f2", 1,0,0,0, 0,0,0,1,0, \
192 ALIASES3(Reg_F2, Reg_F3, Reg_F2F3)) \ 224 ALIASES3(Reg_F2, Reg_F3, Reg_F2F3)) \
193 X(Reg_F4F5, 4, "f4, f5", 1,0,0,0, 0,0,0,1,0, \ 225 X(Reg_F4F5, 4, "f4", 1,0,0,0, 0,0,0,1,0, \
194 ALIASES3(Reg_F4, Reg_F5, Reg_F4F5)) \ 226 ALIASES3(Reg_F4, Reg_F5, Reg_F4F5)) \
195 X(Reg_F6F7, 6, "f6, f7", 1,0,0,0, 0,0,0,1,0, \ 227 X(Reg_F6F7, 6, "f6", 1,0,0,0, 0,0,0,1,0, \
196 ALIASES3(Reg_F6, Reg_F7, Reg_F6F7)) \ 228 ALIASES3(Reg_F6, Reg_F7, Reg_F6F7)) \
197 X(Reg_F8F9, 8, "f8, f9", 1,0,0,0, 0,0,0,1,0, \ 229 X(Reg_F8F9, 8, "f8", 1,0,0,0, 0,0,0,1,0, \
198 ALIASES3(Reg_F8, Reg_F9, Reg_F8F9)) \ 230 ALIASES3(Reg_F8, Reg_F9, Reg_F8F9)) \
199 X(Reg_F10F11, 10, "f10, f11", 1,0,0,0, 0,0,0,1,0, \ 231 X(Reg_F10F11, 10, "f10", 1,0,0,0, 0,0,0,1,0, \
200 ALIASES3(Reg_F10, Reg_F11, Reg_F10F11)) \ 232 ALIASES3(Reg_F10, Reg_F11, Reg_F10F11)) \
201 X(Reg_F12F13, 12, "f12, f13", 1,0,0,0, 0,0,0,1,0, \ 233 X(Reg_F12F13, 12, "f12", 1,0,0,0, 0,0,0,1,0, \
202 ALIASES3(Reg_F12, Reg_F13, Reg_F12F13)) \ 234 ALIASES3(Reg_F12, Reg_F13, Reg_F12F13)) \
203 X(Reg_F14F15, 14, "f14, f15", 1,0,0,0, 0,0,0,1,0, \ 235 X(Reg_F14F15, 14, "f14", 1,0,0,0, 0,0,0,1,0, \
204 ALIASES3(Reg_F14, Reg_F15, Reg_F14F15)) \ 236 ALIASES3(Reg_F14, Reg_F15, Reg_F14F15)) \
205 X(Reg_F16F17, 16, "f16, f17", 1,0,0,0, 0,0,0,1,0, \ 237 X(Reg_F16F17, 16, "f16", 1,0,0,0, 0,0,0,1,0, \
206 ALIASES3(Reg_F16, Reg_F17, Reg_F16F17)) \ 238 ALIASES3(Reg_F16, Reg_F17, Reg_F16F17)) \
207 X(Reg_F18F19, 18, "f18, f19", 1,0,0,0, 0,0,0,1,0, \ 239 X(Reg_F18F19, 18, "f18", 1,0,0,0, 0,0,0,1,0, \
208 ALIASES3(Reg_F18, Reg_F19, Reg_F18F19)) \ 240 ALIASES3(Reg_F18, Reg_F19, Reg_F18F19)) \
209 X(Reg_F20F21, 20, "f20, f21", 1,0,0,0, 0,0,0,1,0, \ 241 X(Reg_F20F21, 20, "f20", 1,0,0,0, 0,0,0,1,0, \
210 ALIASES3(Reg_F20, Reg_F21, Reg_F20F21)) \ 242 ALIASES3(Reg_F20, Reg_F21, Reg_F20F21)) \
211 X(Reg_F22F23, 22, "f22, f23", 1,0,0,0, 0,0,0,1,0, \ 243 X(Reg_F22F23, 22, "f22", 1,0,0,0, 0,0,0,1,0, \
212 ALIASES3(Reg_F22, Reg_F23, Reg_F22F23)) \ 244 ALIASES3(Reg_F22, Reg_F23, Reg_F22F23)) \
213 X(Reg_F24F25, 24, "f24, f25", 1,0,0,0, 0,0,0,1,0, \ 245 X(Reg_F24F25, 24, "f24", 1,0,0,0, 0,0,0,1,0, \
214 ALIASES3(Reg_F24, Reg_F25, Reg_F24F25)) \ 246 ALIASES3(Reg_F24, Reg_F25, Reg_F24F25)) \
215 X(Reg_F26F27, 26, "f26, f27", 1,0,0,0, 0,0,0,1,0, \ 247 X(Reg_F26F27, 26, "f26", 1,0,0,0, 0,0,0,1,0, \
216 ALIASES3(Reg_F26, Reg_F27, Reg_F26F27)) \ 248 ALIASES3(Reg_F26, Reg_F27, Reg_F26F27)) \
217 X(Reg_F28F29, 28, "f28, f29", 1,0,0,0, 0,0,0,1,0, \ 249 X(Reg_F28F29, 28, "f28", 1,0,0,0, 0,0,0,1,0, \
218 ALIASES3(Reg_F28, Reg_F29, Reg_F28F29)) \ 250 ALIASES3(Reg_F28, Reg_F29, Reg_F28F29)) \
219 X(Reg_F30F31, 30, "f30, f31", 1,0,0,0, 0,0,0,1,0, \ 251 X(Reg_F30F31, 30, "f30", 1,0,0,0, 0,0,0,1,0, \
220 ALIASES3(Reg_F30, Reg_F31, Reg_F30F31)) 252 ALIASES3(Reg_F30, Reg_F31, Reg_F30F31))
221 253
222 // We also provide a combined table, so that there is a namespace where 254 // We also provide a combined table, so that there is a namespace where
223 // all of the registers are considered and have distinct numberings. 255 // all of the registers are considered and have distinct numberings.
224 // This is in contrast to the above, where the "encode" is based on how 256 // This is in contrast to the above, where the "encode" is based on how
225 // the register numbers will be encoded in binaries and values can overlap. 257 // the register numbers will be encoded in binaries and values can overlap.
226 #define REGMIPS32_TABLE \ 258 #define REGMIPS32_TABLE \
227 /* val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ 259 /* val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \
228 isFP32, isFP64, isVec128, alias_init */ \ 260 isFP32, isFP64, isVec128, alias_init */ \
229 REGMIPS32_GPR_TABLE \ 261 REGMIPS32_GPR_TABLE \
(...skipping 23 matching lines...) Expand all
253 X(NEZ, EQZ, "nez") /* signed not equal to zero */ \ 285 X(NEZ, EQZ, "nez") /* signed not equal to zero */ \
254 X(GEZ, LTZ, "gez") /* signed greater than or equal to zero */ \ 286 X(GEZ, LTZ, "gez") /* signed greater than or equal to zero */ \
255 X(LTZ, GEZ, "ltz") /* signed less than to zero */ \ 287 X(LTZ, GEZ, "ltz") /* signed less than to zero */ \
256 X(GTZ, LEZ, "gtz") /* signed greater than to zero */ \ 288 X(GTZ, LEZ, "gtz") /* signed greater than to zero */ \
257 X(LEZ, GTZ, "lez") /* signed less than or equal to zero */ \ 289 X(LEZ, GTZ, "lez") /* signed less than or equal to zero */ \
258 X(AL, kNone, "") /* always (unconditional) */ \ 290 X(AL, kNone, "") /* always (unconditional) */ \
259 X(kNone, kNone, "??") /* special condition / none */ 291 X(kNone, kNone, "??") /* special condition / none */
260 //#define X(tag, opp, emit) 292 //#define X(tag, opp, emit)
261 293
262 #endif // SUBZERO_SRC_ICEINSTMIPS32_DEF 294 #endif // SUBZERO_SRC_ICEINSTMIPS32_DEF
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