Subzero, MIPS32: Handling floating point instructions fadd, fsub, fmul, fdiv

src/IceTargetLoweringMIPS32.cpp

 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost
@@ skipping 1236 matching lines @@
     lowerInt64Arithmetic(Instr, Instr->getDest(), Src0, Src1);
     return;
   }
   if (isVectorType(Dest->getType())) {
     UnimplementedLoweringError(this, Instr);
     return;
   }
   switch (Instr->getOp()) {
   default:
     break;
-  case InstArithmetic::Fadd:
-  case InstArithmetic::Fsub:
-  case InstArithmetic::Fmul:
-  case InstArithmetic::Fdiv:
   case InstArithmetic::Frem:
     UnimplementedLoweringError(this, Instr);
     return;
   }
 
   // At this point Dest->getType() is non-i64 scalar
 
   Variable *T = makeReg(Dest->getType());
   Variable *Src0R = legalizeToReg(Src0);
   Variable *Src1R = legalizeToReg(Src1);
@@ skipping 62 matching lines @@
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Srem: {
     auto *T_Zero = I32Reg(RegMIPS32::Reg_ZERO);
     _div(T_Zero, Src0R, Src1R);
     _mfhi(T, T_Zero);
     _mov(Dest, T);
     return;
   }
-  case InstArithmetic::Fadd:
+  case InstArithmetic::Fadd: {
+    if (DestTy == IceType_f32) {
+      _add_s(T, Src0R, Src1R);
+      _mov(Dest, T);
+      return;
+    }
+    if (DestTy == IceType_f64) {
+      _add_d(T, Src0R, Src1R);
+      _mov(Dest, T);
+      return;
+    }
     break;
+  }
   case InstArithmetic::Fsub:
+    if (DestTy == IceType_f32) {
+      _sub_s(T, Src0R, Src1R);
+      _mov(Dest, T);
+      return;
+    }
+    if (DestTy == IceType_f64) {
+      _sub_d(T, Src0R, Src1R);
+      _mov(Dest, T);
+      return;
+    }
     break;
   case InstArithmetic::Fmul:
+    if (DestTy == IceType_f32) {
+      _mul_s(T, Src0R, Src1R);
+      _mov(Dest, T);
+      return;
+    }
+    if (DestTy == IceType_f64) {
+      _mul_d(T, Src0R, Src1R);
+      _mov(Dest, T);
+      return;
+    }
     break;
   case InstArithmetic::Fdiv:
+    if (DestTy == IceType_f32) {
+      _div_s(T, Src0R, Src1R);
+      _mov(Dest, T);
+      return;
+    }
+    if (DestTy == IceType_f64) {
+      _div_d(T, Src0R, Src1R);
+      _mov(Dest, T);
+      return;
+    }
     break;
   case InstArithmetic::Frem:
     break;
   }
   UnimplementedLoweringError(this, Instr);
 }
 
 void TargetMIPS32::lowerAssign(const InstAssign *Instr) {
   Variable *Dest = Instr->getDest();
   Operand *Src0 = Instr->getSrc(0);
@@ skipping 701 matching lines @@
       break;
     }
     case IceType_i64: {
       Src0 = legalizeUndef(Src0);
       Variable *R0 = legalizeToReg(loOperand(Src0), RegMIPS32::Reg_V0);
       Variable *R1 = legalizeToReg(hiOperand(Src0), RegMIPS32::Reg_V1);
       Reg = R0;
       Context.insert<InstFakeUse>(R1);
       break;
     }
-
     default:
       UnimplementedLoweringError(this, Instr);
     }
   }
   _ret(getPhysicalRegister(RegMIPS32::Reg_RA), Reg);
 }
 
 void TargetMIPS32::lowerSelect(const InstSelect *Instr) {
   UnimplementedLoweringError(this, Instr);
 }
@@ skipping 102 matching lines @@
     return;
 }
 
 // Helper for legalize() to emit the right code to lower an operand to a
 // register of the appropriate type.
 Variable *TargetMIPS32::copyToReg(Operand *Src, RegNumT RegNum) {
   Type Ty = Src->getType();
   Variable *Reg = makeReg(Ty, RegNum);
   if (isVectorType(Ty)) {
     UnimplementedError(getFlags());
-  } else if (isFloatingType(Ty)) {
-    (Ty == IceType_f32) ? _mov_s(Reg, llvm::dyn_cast<Variable>(Src))
-                        : _mov_d(Reg, llvm::dyn_cast<Variable>(Src));
   } else {
     // Mov's Src operand can really only be the flexible second operand type
     // or a register. Users should guarantee that.
     _mov(Reg, Src);
   }
   return Reg;
 }
 
 Operand *TargetMIPS32::legalize(Operand *From, LegalMask Allowed,
                                 RegNumT RegNum) {
@@ skipping 153 matching lines @@
   Str << "\t.set\t"
       << "nomips16\n";
 }
 
 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM];
 
 } // end of namespace MIPS32
 } // end of namespace Ice