Chromium Code Reviews| OLD | NEW |
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| 1 // | 1 // |
| 2 // The Subzero Code Generator | 2 // The Subzero Code Generator |
| 3 // | 3 // |
| 4 // This file is distributed under the University of Illinois Open Source | 4 // This file is distributed under the University of Illinois Open Source |
| 5 // License. See LICENSE.TXT for details. | 5 // License. See LICENSE.TXT for details. |
| 6 // | 6 // |
| 7 //===----------------------------------------------------------------------===// | 7 //===----------------------------------------------------------------------===// |
| 8 /// | 8 /// |
| 9 /// \file | 9 /// \file |
| 10 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost | 10 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost |
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| 403 Context.setInsertPoint(Context.getCur()); | 403 Context.setInsertPoint(Context.getCur()); |
| 404 for (SizeT I = 0, E = Args.size(); I < E; ++I) { | 404 for (SizeT I = 0, E = Args.size(); I < E; ++I) { |
| 405 Variable *Arg = Args[I]; | 405 Variable *Arg = Args[I]; |
| 406 Type Ty = Arg->getType(); | 406 Type Ty = Arg->getType(); |
| 407 // TODO(rkotler): handle float/vector types. | 407 // TODO(rkotler): handle float/vector types. |
| 408 if (isVectorType(Ty)) { | 408 if (isVectorType(Ty)) { |
| 409 UnimplementedError(getFlags()); | 409 UnimplementedError(getFlags()); |
| 410 continue; | 410 continue; |
| 411 } | 411 } |
| 412 if (isFloatingType(Ty)) { | 412 if (isFloatingType(Ty)) { |
| 413 UnimplementedError(getFlags()); | 413 UnimplementedError(getFlags()); |
|
Jim Stichnoth
2016/06/01 13:52:13
When I run the updated lit test, I'm getting a fai
obucinac
2016/06/01 14:21:16
This is because calling convention is still not in
Jim Stichnoth
2016/06/01 21:22:08
Hmm, I get the same unimplemented error in this pl
| |
| 414 continue; | 414 continue; |
| 415 } | 415 } |
| 416 if (Ty == IceType_i64) { | 416 if (Ty == IceType_i64) { |
| 417 if (NumGPRRegsUsed >= MIPS32_MAX_GPR_ARG) | 417 if (NumGPRRegsUsed >= MIPS32_MAX_GPR_ARG) |
| 418 continue; | 418 continue; |
| 419 auto RegLo = RegNumT::fixme(RegMIPS32::Reg_A0 + NumGPRRegsUsed); | 419 auto RegLo = RegNumT::fixme(RegMIPS32::Reg_A0 + NumGPRRegsUsed); |
| 420 auto RegHi = RegNumT::fixme(RegLo + 1); | 420 auto RegHi = RegNumT::fixme(RegLo + 1); |
| 421 ++NumGPRRegsUsed; | 421 ++NumGPRRegsUsed; |
| 422 // Always start i64 registers at an even register, so this may end | 422 // Always start i64 registers at an even register, so this may end |
| 423 // up padding away a register. | 423 // up padding away a register. |
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| 683 Operand *Src0 = legalizeUndef(Instr->getSrc(0)); | 683 Operand *Src0 = legalizeUndef(Instr->getSrc(0)); |
| 684 Operand *Src1 = legalizeUndef(Instr->getSrc(1)); | 684 Operand *Src1 = legalizeUndef(Instr->getSrc(1)); |
| 685 if (DestTy == IceType_i64) { | 685 if (DestTy == IceType_i64) { |
| 686 lowerInt64Arithmetic(Instr, Instr->getDest(), Src0, Src1); | 686 lowerInt64Arithmetic(Instr, Instr->getDest(), Src0, Src1); |
| 687 return; | 687 return; |
| 688 } | 688 } |
| 689 if (isVectorType(Dest->getType())) { | 689 if (isVectorType(Dest->getType())) { |
| 690 UnimplementedLoweringError(this, Instr); | 690 UnimplementedLoweringError(this, Instr); |
| 691 return; | 691 return; |
| 692 } | 692 } |
| 693 switch (Instr->getOp()) { | |
| 694 default: | |
| 695 break; | |
| 696 case InstArithmetic::Fadd: | |
| 697 case InstArithmetic::Fsub: | |
| 698 case InstArithmetic::Fmul: | |
| 699 case InstArithmetic::Fdiv: | |
| 700 case InstArithmetic::Frem: | |
| 701 UnimplementedLoweringError(this, Instr); | |
| 702 return; | |
| 703 } | |
| 704 | 693 |
| 705 // At this point Dest->getType() is non-i64 scalar | 694 // At this point Dest->getType() is non-i64 scalar |
| 706 | 695 |
| 707 Variable *T = makeReg(Dest->getType()); | 696 Variable *T = makeReg(Dest->getType()); |
| 708 Variable *Src0R = legalizeToReg(Src0); | 697 Variable *Src0R = legalizeToReg(Src0); |
| 709 Variable *Src1R = legalizeToReg(Src1); | 698 Variable *Src1R = legalizeToReg(Src1); |
| 710 | 699 |
| 711 switch (Instr->getOp()) { | 700 switch (Instr->getOp()) { |
| 712 case InstArithmetic::_num: | 701 case InstArithmetic::_num: |
| 713 break; | 702 break; |
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| 772 _mov(Dest, T); | 761 _mov(Dest, T); |
| 773 return; | 762 return; |
| 774 } | 763 } |
| 775 case InstArithmetic::Srem: { | 764 case InstArithmetic::Srem: { |
| 776 auto *T_Zero = I32Reg(RegMIPS32::Reg_ZERO); | 765 auto *T_Zero = I32Reg(RegMIPS32::Reg_ZERO); |
| 777 _div(T_Zero, Src0R, Src1R); | 766 _div(T_Zero, Src0R, Src1R); |
| 778 _mfhi(T, T_Zero); | 767 _mfhi(T, T_Zero); |
| 779 _mov(Dest, T); | 768 _mov(Dest, T); |
| 780 return; | 769 return; |
| 781 } | 770 } |
| 782 case InstArithmetic::Fadd: | 771 case InstArithmetic::Fadd: { |
| 772 if (DestTy == IceType_f32) { | |
| 773 _add_s(T, Src0R, Src1R); | |
| 774 _mov_s(Dest, T); | |
| 775 return; | |
| 776 } | |
| 777 if (DestTy == IceType_f64) { | |
| 778 _add_d(T, Src0R, Src1R); | |
| 779 _mov_d(Dest, T); | |
| 780 return; | |
| 781 } | |
| 783 break; | 782 break; |
| 783 } | |
| 784 case InstArithmetic::Fsub: | 784 case InstArithmetic::Fsub: |
| 785 if (DestTy == IceType_f32) { | |
| 786 _sub_s(T, Src0R, Src1R); | |
| 787 _mov_s(Dest, T); | |
| 788 return; | |
| 789 } | |
| 790 if (DestTy == IceType_f64) { | |
| 791 _sub_d(T, Src0R, Src1R); | |
| 792 _mov_d(Dest, T); | |
| 793 return; | |
| 794 } | |
| 785 break; | 795 break; |
| 786 case InstArithmetic::Fmul: | 796 case InstArithmetic::Fmul: |
| 797 if (DestTy == IceType_f32) { | |
| 798 _mul_s(T, Src0R, Src1R); | |
| 799 _mov_s(Dest, T); | |
| 800 return; | |
| 801 } | |
| 802 if (DestTy == IceType_f64) { | |
| 803 _mul_d(T, Src0R, Src1R); | |
| 804 _mov_d(Dest, T); | |
| 805 return; | |
| 806 } | |
| 787 break; | 807 break; |
| 788 case InstArithmetic::Fdiv: | 808 case InstArithmetic::Fdiv: |
| 809 if (DestTy == IceType_f32) { | |
| 810 _div_s(T, Src0R, Src1R); | |
| 811 _mov_s(Dest, T); | |
| 812 return; | |
| 813 } | |
| 814 if (DestTy == IceType_f64) { | |
| 815 _div_d(T, Src0R, Src1R); | |
| 816 _mov_d(Dest, T); | |
| 817 return; | |
| 818 } | |
| 789 break; | 819 break; |
| 790 case InstArithmetic::Frem: | 820 case InstArithmetic::Frem: |
|
Jim Stichnoth
2016/06/01 13:52:13
For frem, all the other targets create a call to t
obucinac
2016/06/01 14:21:16
Acknowledged.
| |
| 791 break; | 821 break; |
| 792 } | 822 } |
| 793 UnimplementedLoweringError(this, Instr); | 823 UnimplementedLoweringError(this, Instr); |
| 794 } | 824 } |
| 795 | 825 |
| 796 void TargetMIPS32::lowerAssign(const InstAssign *Instr) { | 826 void TargetMIPS32::lowerAssign(const InstAssign *Instr) { |
| 797 Variable *Dest = Instr->getDest(); | 827 Variable *Dest = Instr->getDest(); |
| 798 Operand *Src0 = Instr->getSrc(0); | 828 Operand *Src0 = Instr->getSrc(0); |
| 799 assert(Dest->getType() == Src0->getType()); | 829 assert(Dest->getType() == Src0->getType()); |
| 800 if (Dest->getType() == IceType_i64) { | 830 if (Dest->getType() == IceType_i64) { |
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| 1668 Str << "\t.set\t" | 1698 Str << "\t.set\t" |
| 1669 << "nomips16\n"; | 1699 << "nomips16\n"; |
| 1670 } | 1700 } |
| 1671 | 1701 |
| 1672 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM]; | 1702 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM]; |
| 1673 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM]; | 1703 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM]; |
| 1674 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM]; | 1704 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM]; |
| 1675 | 1705 |
| 1676 } // end of namespace MIPS32 | 1706 } // end of namespace MIPS32 |
| 1677 } // end of namespace Ice | 1707 } // end of namespace Ice |
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