[Turbofan] Add ia32 support for 4 and 16 byte moves and swaps.

[Turbofan] Add ia32 support for 4 and 16 byte moves and swaps.
- Adds move/swap handling for 4 and 16 bytes to ia32.
- Register allocator now only requests 4 bytes for floats on ia32 and arm.
- We probably need similar support in mips.

LOG=N
BUG=v8:4124
Committed: https://crrev.com/26ecb4a1d775d506700d20542f723e8baeb37e48
Cr-Commit-Position: refs/heads/master@{#37714}

[bbudge, 2016-07-12 15:25:09]

bbudge@chromium.org changed reviewers:
+ bmeurer@chromium.org

[bbudge, 2016-07-12 15:31:44]

bbudge@chromium.org changed reviewers:
- bmeurer@chromium.org

[bbudge, 2016-07-12 15:31:44]

Hold off on review for now.

[bbudge, 2016-07-12 17:10:44]

Description was changed from

==========
Turbofan: floats occupy only 4 bytes in a spill slot.
- Register allocator only requests 4 bytes for floats when allocating
a spill slot.
- Adds move/swap handling for arm FloatRegisters.

LOG=N
BUG=v8:4124
==========

to

==========
[Turbofan] Add ia32 support for 4 and 16 byte moves and swaps.
- Adds move/swap handling for 4 and 16 bytes to ia32.
- Register allocator now only requests 4 bytes for floats on ia32 and arm.
- We probably need similar support in mips.


LOG=N
BUG=v8:4124
==========

[bbudge, 2016-07-12 17:10:44]

bbudge@chromium.org changed reviewers:
+ bmeurer@chromium.org

[bbudge, 2016-07-12 17:11:05]

On 2016/07/12 15:31:44, bbudge wrote:
> Hold off on review for now.

OK, PTAL

[Benedikt Meurer, 2016-07-12 17:41:49]

https://codereview.chromium.org/2027043002/diff/40001/src/compiler/ia32/code-...
File src/compiler/ia32/code-generator-ia32.cc (right):

https://codereview.chromium.org/2027043002/diff/40001/src/compiler/ia32/code-...
src/compiler/ia32/code-generator-ia32.cc:2023: __ movdqu(dst, src);
Why don't we also use movupd here, similar to x64? Or matching the movaps above
use movups here? The intel manual seems to suggest that movdqu should only be
used for integers. If in doubt, prefer movups since it has shorter encoding
IIRC.

https://codereview.chromium.org/2027043002/diff/40001/src/compiler/ia32/code-...
src/compiler/ia32/code-generator-ia32.cc:2038: __ movdqu(dst, src);
See above.

https://codereview.chromium.org/2027043002/diff/40001/src/compiler/ia32/code-...
src/compiler/ia32/code-generator-ia32.cc:2050: __ movdqu(kScratchDoubleReg,
src);
See above.

[bbudge, 2016-07-12 17:50:30]

I need to add disassembler support for movups.

https://codereview.chromium.org/2027043002/diff/40001/src/compiler/ia32/code-...
File src/compiler/ia32/code-generator-ia32.cc (right):

https://codereview.chromium.org/2027043002/diff/40001/src/compiler/ia32/code-...
src/compiler/ia32/code-generator-ia32.cc:2023: __ movdqu(dst, src);
On 2016/07/12 17:41:49, Benedikt Meurer wrote:
> Why don't we also use movupd here, similar to x64? Or matching the movaps
above
> use movups here? The intel manual seems to suggest that movdqu should only be
> used for integers. If in doubt, prefer movups since it has shorter encoding
> IIRC.

It's funny but I did that first, then noticed that movdqu was already
implemented so removed movups. Putting it back. I will also add disassembler
support.

https://codereview.chromium.org/2027043002/diff/40001/src/compiler/ia32/code-...
src/compiler/ia32/code-generator-ia32.cc:2038: __ movdqu(dst, src);
On 2016/07/12 17:41:49, Benedikt Meurer wrote:
> See above.

Done.

https://codereview.chromium.org/2027043002/diff/40001/src/compiler/ia32/code-...
src/compiler/ia32/code-generator-ia32.cc:2050: __ movdqu(kScratchDoubleReg,
src);
On 2016/07/12 17:41:49, Benedikt Meurer wrote:
> See above.

Done.

[Benedikt Meurer, 2016-07-13 04:13:06]

Thanks, LGTM.

[bbudge, 2016-07-13 13:49:55]

The CQ bit was checked by bbudge@chromium.org

[commit-bot: I haz the power, 2016-07-13 13:50:06]

CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2016-07-13 13:53:08]

Description was changed from

==========
[Turbofan] Add ia32 support for 4 and 16 byte moves and swaps.
- Adds move/swap handling for 4 and 16 bytes to ia32.
- Register allocator now only requests 4 bytes for floats on ia32 and arm.
- We probably need similar support in mips.


LOG=N
BUG=v8:4124
==========

to

==========
[Turbofan] Add ia32 support for 4 and 16 byte moves and swaps.
- Adds move/swap handling for 4 and 16 bytes to ia32.
- Register allocator now only requests 4 bytes for floats on ia32 and arm.
- We probably need similar support in mips.


LOG=N
BUG=v8:4124
==========

[commit-bot: I haz the power, 2016-07-13 13:53:08]

Committed patchset #5 (id:80001)

[commit-bot: I haz the power, 2016-07-13 13:54:48]

Description was changed from

==========
[Turbofan] Add ia32 support for 4 and 16 byte moves and swaps.
- Adds move/swap handling for 4 and 16 bytes to ia32.
- Register allocator now only requests 4 bytes for floats on ia32 and arm.
- We probably need similar support in mips.


LOG=N
BUG=v8:4124
==========

to

==========
[Turbofan] Add ia32 support for 4 and 16 byte moves and swaps.
- Adds move/swap handling for 4 and 16 bytes to ia32.
- Register allocator now only requests 4 bytes for floats on ia32 and arm.
- We probably need similar support in mips.

LOG=N
BUG=v8:4124

Committed: https://crrev.com/26ecb4a1d775d506700d20542f723e8baeb37e48
Cr-Commit-Position: refs/heads/master@{#37714}
==========

[commit-bot: I haz the power, 2016-07-13 13:54:49]

Patchset 5 (id:??) landed as
https://crrev.com/26ecb4a1d775d506700d20542f723e8baeb37e48
Cr-Commit-Position: refs/heads/master@{#37714}