[Subzero][MIPS32] Add argument handling in LowerCall

src/IceTargetLoweringMIPS32.cpp

 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost
@@ skipping 46 matching lines @@
 namespace Ice {
 namespace MIPS32 {
 
 using llvm::isInt;
 
 namespace {
 
 // The maximum number of arguments to pass in GPR registers.
 constexpr uint32_t MIPS32_MAX_GPR_ARG = 4;
 
+std::array<RegNumT, MIPS32_MAX_GPR_ARG> GPRArgInitializer;
+std::array<RegNumT, MIPS32_MAX_GPR_ARG / 2> I64ArgInitializer;
+
 const char *getRegClassName(RegClass C) {
   auto ClassNum = static_cast<RegClassMIPS32>(C);
   assert(ClassNum < RCMIPS32_NUM);
   switch (ClassNum) {
   default:
     assert(C < RC_Target);
     return regClassString(C);
     // Add handling of new register classes below.
   }
 }
 
+// Stack alignment
+constexpr uint32_t MIPS32_STACK_ALIGNMENT_BYTES = 16;
+
+// Value is in bytes. Return Value adjusted to the next highest multiple of the
+// stack alignment.
+uint32_t applyStackAlignment(uint32_t Value) {
+  return Utils::applyAlignment(Value, MIPS32_STACK_ALIGNMENT_BYTES);
+}
+
+// Value is in bytes. Return Value adjusted to the next highest multiple of the
+// stack alignment required for the given type.
+uint32_t applyStackAlignmentTy(uint32_t Value, Type Ty) {
+  size_t typeAlignInBytes = typeWidthInBytes(Ty);
+  if (isVectorType(Ty))
+    typeAlignInBytes = 8;
+  return Utils::applyAlignment(Value, typeAlignInBytes);
+}
+
 } // end of anonymous namespace
 
 TargetMIPS32::TargetMIPS32(Cfg *Func) : TargetLowering(Func) {}
 
 void TargetMIPS32::staticInit(GlobalContext *Ctx) {
   (void)Ctx;
   RegNumT::setLimit(RegMIPS32::Reg_NUM);
   SmallBitVector IntegerRegisters(RegMIPS32::Reg_NUM);
   SmallBitVector I64PairRegisters(RegMIPS32::Reg_NUM);
   SmallBitVector Float32Registers(RegMIPS32::Reg_NUM);
@@ skipping 10 matching lines @@
   RegisterAliases[RegMIPS32::val].resize(RegMIPS32::Reg_NUM);                  \
   for (SizeT RegAlias : alias_init) {                                          \
     assert(!RegisterAliases[RegMIPS32::val][RegAlias] &&                       \
            "Duplicate alias for " #val);                                       \
     RegisterAliases[RegMIPS32::val].set(RegAlias);                             \
   }                                                                            \
   RegisterAliases[RegMIPS32::val].resize(RegMIPS32::Reg_NUM);                  \
   assert(RegisterAliases[RegMIPS32::val][RegMIPS32::val]);
   REGMIPS32_TABLE;
 #undef X
+
+  for (size_t i = 0; i < MIPS32_MAX_GPR_ARG; i++)
+    GPRArgInitializer[i] = RegNumT::fixme(RegMIPS32::Reg_A0 + i);
+
+  for (size_t i = 0; i < MIPS32_MAX_GPR_ARG / 2; i++)
+    I64ArgInitializer[i] = RegNumT::fixme(RegMIPS32::Reg_A0A1 + i);
+
   TypeToRegisterSet[IceType_void] = InvalidRegisters;
   TypeToRegisterSet[IceType_i1] = IntegerRegisters;
   TypeToRegisterSet[IceType_i8] = IntegerRegisters;
   TypeToRegisterSet[IceType_i16] = IntegerRegisters;
   TypeToRegisterSet[IceType_i32] = IntegerRegisters;
   TypeToRegisterSet[IceType_i64] = IntegerRegisters;
   TypeToRegisterSet[IceType_f32] = Float32Registers;
   TypeToRegisterSet[IceType_f64] = Float64Registers;
   TypeToRegisterSet[IceType_v4i1] = VectorRegisters;
   TypeToRegisterSet[IceType_v8i1] = VectorRegisters;
@@ skipping 264 matching lines @@
     return;
   } else {
     int32_t Offset = Var->getStackOffset();
     Str << Offset;
     Str << "($" << getRegName(getFrameOrStackReg(), FrameSPTy);
     Str << ")";
   }
   UnimplementedError(getFlags());
 }
 
+TargetMIPS32::CallingConv::CallingConv()
+    : GPRegsUsed(RegMIPS32::Reg_NUM),
+      GPRArgs(GPRArgInitializer.rbegin(), GPRArgInitializer.rend()),
+      I64Args(I64ArgInitializer.rbegin(), I64ArgInitializer.rend()) {}
+
+bool TargetMIPS32::CallingConv::argInGPR(Type Ty, RegNumT *Reg) {
+  CfgVector<RegNumT> *Source;
+
+  switch (Ty) {
+  default: {
+    assert(isScalarIntegerType(Ty));
+    Source = &GPRArgs;
+  } break;
+  case IceType_i64: {
+    Source = &I64Args;
+  } break;
+  }
+
+  discardUnavailableGPRsAndTheirAliases(Source);
+
+  if (Source->empty()) {
+    GPRegsUsed.set();
+    return false;
+  }
+
+  *Reg = Source->back();
+  // Note that we don't Source->pop_back() here. This is intentional. Notice how
+  // we mark all of Reg's aliases as Used. So, for the next argument,
+  // Source->back() is marked as unavailable, and it is thus implicitly popped
+  // from the stack.
+  GPRegsUsed |= RegisterAliases[*Reg];
+  return true;
+}
+
+// GPR are not packed when passing parameters. Thus, a function foo(i32, i64,
+// i32) will have the first argument in r0, the second in r2-r3, and the third
+// on the stack. To model this behavior, whenever we pop a register from Regs,
+// we remove all of its aliases from the pool of available GPRs. This has the
+// effect of computing the "closure" on the GPR registers.
+void TargetMIPS32::CallingConv::discardUnavailableGPRsAndTheirAliases(
+    CfgVector<RegNumT> *Regs) {
+  while (!Regs->empty() && GPRegsUsed[Regs->back()]) {
+    GPRegsUsed |= RegisterAliases[Regs->back()];
+    Regs->pop_back();
+  }
+}
+
 void TargetMIPS32::lowerArguments() {
   VarList &Args = Func->getArgs();
   // We are only handling integer registers for now. The Mips o32 ABI is
   // somewhat complex but will be implemented in its totality through follow
   // on patches.
   //
   unsigned NumGPRRegsUsed = 0;
   // For each register argument, replace Arg in the argument list with the
   // home register.  Then generate an instruction in the prolog to copy the
   // home register to the assigned location of Arg.
@@ skipping 507 matching lines @@
     case InstIcmp::Sle: {
       _slt(DestT, Src1R, Src0R);
       _br(TargetTrue, TargetFalse, DestT, CondMIPS32::Cond::NEZ);
       break;
     }
     }
   }
 }
 
 void TargetMIPS32::lowerCall(const InstCall *Instr) {
-  // TODO(rkotler): assign arguments to registers and stack. Also reserve stack.
-  if (Instr->getNumArgs()) {
-    UnimplementedLoweringError(this, Instr);
-    return;
+  NeedsStackAlignment = true;
+
+  //  Assign arguments to registers and stack. Also reserve stack.
+  TargetMIPS32::CallingConv CC;
+
+  // Pair of Arg Operand -> GPR number assignments.
+  llvm::SmallVector<std::pair<Operand *, RegNumT>, MIPS32_MAX_GPR_ARG> GPRArgs;
+
+  // Pair of Arg Operand -> stack offset.
+  llvm::SmallVector<std::pair<Operand *, int32_t>, 8> StackArgs;
+  size_t ParameterAreaSizeBytes = 16;
+
+  // Classify each argument operand according to the location where the
+  // argument is passed.
+
+  for (SizeT i = 0, NumArgs = Instr->getNumArgs(); i < NumArgs; ++i) {
+    Operand *Arg = legalizeUndef(Instr->getArg(i));
+    const Type Ty = Arg->getType();
+    bool InReg = false;
+    RegNumT Reg;
+    if (isScalarIntegerType(Ty)) {
+      InReg = CC.argInGPR(Ty, &Reg);
+    } else {
+      // TODO(mohit.bhakkad) : Handle arguments of type other than
+      // ScalarIntegerType
+      UnimplementedLoweringError(this, Instr);
+      return;
+    }
+
+    if (!InReg) {
+      ParameterAreaSizeBytes =
+          applyStackAlignmentTy(ParameterAreaSizeBytes, Ty);
+      StackArgs.push_back(std::make_pair(Arg, ParameterAreaSizeBytes));
+      ParameterAreaSizeBytes += typeWidthInBytesOnStack(Ty);
+      continue;
+    }
+
+    if (Ty == IceType_i64) {
+      Operand *Lo = loOperand(Arg);
+      Operand *Hi = hiOperand(Arg);
+      GPRArgs.push_back(
+          std::make_pair(Lo, RegMIPS32::getI64PairFirstGPRNum(Reg)));
+      GPRArgs.push_back(
+          std::make_pair(Hi, RegMIPS32::getI64PairSecondGPRNum(Reg)));
+    } else if (isScalarIntegerType(Ty)) {
+      GPRArgs.push_back(std::make_pair(Arg, Reg));
+    } else {
+      // TODO(mohit.bhakkad) : Handle arguments of type other than
+      // ScalarIntegerType
+      UnimplementedLoweringError(this, Instr);
+      return;
+    }
   }
+
+  // Adjust the parameter area so that the stack is aligned. It is assumed that
+  // the stack is already aligned at the start of the calling sequence.
+  ParameterAreaSizeBytes = applyStackAlignment(ParameterAreaSizeBytes);
+
+  // Copy arguments that are passed on the stack to the appropriate stack
+  // locations.
+  Variable *SP = getPhysicalRegister(RegMIPS32::Reg_SP);
+  for (auto &StackArg : StackArgs) {
+    ConstantInteger32 *Loc =
+        llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(StackArg.second));
+    Type Ty = StackArg.first->getType();
+    OperandMIPS32Mem *Addr;
+    constexpr bool SignExt = false;
+    if (OperandMIPS32Mem::canHoldOffset(Ty, SignExt, StackArg.second)) {
+      Addr = OperandMIPS32Mem::create(Func, Ty, SP, Loc);
+    } else {
+      Variable *NewBase = Func->makeVariable(SP->getType());
+      lowerArithmetic(
+          InstArithmetic::create(Func, InstArithmetic::Add, NewBase, SP, Loc));
+      Addr = formMemoryOperand(NewBase, Ty);
+    }
+    lowerStore(InstStore::create(Func, StackArg.first, Addr));
+  }
+
   // Generate the call instruction.  Assign its result to a temporary with high
   // register allocation weight.
   Variable *Dest = Instr->getDest();
   // ReturnReg doubles as ReturnRegLo as necessary.
   Variable *ReturnReg = nullptr;
   Variable *ReturnRegHi = nullptr;
   if (Dest) {
     switch (Dest->getType()) {
     case IceType_NUM:
       llvm_unreachable("Invalid Call dest type");
@@ skipping 25 matching lines @@
       return;
     }
   }
   Operand *CallTarget = Instr->getCallTarget();
   // Allow ConstantRelocatable to be left alone as a direct call,
   // but force other constants like ConstantInteger32 to be in
   // a register and make it an indirect call.
   if (!llvm::isa<ConstantRelocatable>(CallTarget)) {
     CallTarget = legalize(CallTarget, Legal_Reg);
   }
+
+  // Copy arguments to be passed in registers to the appropriate registers.
+  CfgVector<Variable *> RegArgs;
+  for (auto &GPRArg : GPRArgs) {
+    RegArgs.emplace_back(legalizeToReg(GPRArg.first, GPRArg.second));
+  }
+
+  // Generate a FakeUse of register arguments so that they do not get dead code
+  // eliminated as a result of the FakeKill of scratch registers after the call.
+  // These fake-uses need to be placed here to avoid argument registers from
+  // being used during the legalizeToReg() calls above.
+  for (auto *RegArg : RegArgs) {
+    Context.insert<InstFakeUse>(RegArg);
+  }
+
   Inst *NewCall = InstMIPS32Call::create(Func, ReturnReg, CallTarget);
   Context.insert(NewCall);
   if (ReturnRegHi)
     Context.insert(InstFakeDef::create(Func, ReturnRegHi));
   // Insert a register-kill pseudo instruction.
   Context.insert(InstFakeKill::create(Func, NewCall));
   // Generate a FakeUse to keep the call live if necessary.
   if (Instr->hasSideEffects() && ReturnReg) {
     Context.insert<InstFakeDef>(ReturnReg);
   }
@@ skipping 667 matching lines @@
   Str << "\t.set\t"
       << "nomips16\n";
 }
 
 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM];
 
 } // end of namespace MIPS32
 } // end of namespace Ice