MIPS: Fix '[turbofan] Introduce new operators Float32SubPreserveNan and Float64SubPreserveNan'.

src/mips/macro-assembler-mips.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <limits.h>  // For LONG_MIN, LONG_MAX.
 
 #if V8_TARGET_ARCH_MIPS
 
 #include "src/base/bits.h"
 #include "src/base/division-by-constant.h"
@@ skipping 4697 matching lines @@
   // scratch1 is now effective address of the double element
 
   Register untagged_value = scratch2;
   SmiUntag(untagged_value, value_reg);
   mtc1(untagged_value, f2);
   cvt_d_w(f0, f2);
   sdc1(f0, MemOperand(scratch1, 0));
   bind(&done);
 }
 
+void MacroAssembler::SubNanPreservePayloadAndSign_s(FPURegister fd,
+                                                    FPURegister fs,
+                                                    FPURegister ft) {
+  Label maybe_nan, not_nan2008, nan2008, done;
+  Register scratch1 = t8;
+  Register scratch2 = t9;
+  DoubleRegister double_scratch = f8;
+
+  sub_s(fd, fs, ft);
+  // Check if the result of subtraction is NaN or infinity.
+  sub_s(double_scratch, fd, fd);
+  BranchF32(&done, nullptr, eq, double_scratch, kDoubleRegZero);
+
+  // Check if first operand is a possible NaN.
+  mfc1(scratch1, fs);
+  And(scratch2, scratch1, Operand(FloatConstants::kExponentMask));
+  Branch(&maybe_nan, eq, scratch2, Operand(FloatConstants::kExponentMask));
+  // Check if second operand is a possible NaN.
+  mfc1(scratch1, ft);
+  And(scratch2, scratch1, Operand(FloatConstants::kExponentMask));
+  Branch(&done, ne, scratch2, Operand(FloatConstants::kExponentMask));
+
+  // Check if possible NaN is actually NaN.
+  bind(&maybe_nan);
+  And(scratch2, scratch1, Operand(FloatConstants::kMantissaMask));
+  Branch(&done, eq, scratch2, Operand(zero_reg));
+  // If NaN is found, return it as qNaN with same payload.
+  // Determine the qNaN encoding for the current architecture.
+  LoadRoot(scratch2, Heap::kNanValueRootIndex);
+  ldc1(double_scratch, FieldMemOperand(scratch2, HeapNumber::kValueOffset));
+  Mfhc1(scratch2, double_scratch);
+  And(scratch2, scratch2, Operand(DoubleConstants::kNanTypeMask));
+  // Make NaN quiet.
+  Branch(&nan2008, gt, scratch2, Operand(zero_reg));
+  And(scratch1, scratch1, Operand(~FloatConstants::kNanTypeMask));
+  Branch(&not_nan2008);
+  bind(&nan2008);
+  Or(scratch1, scratch1, Operand(FloatConstants::kNanTypeMask));
+  bind(&not_nan2008);
+  mtc1(scratch1, fd);
+  bind(&done);
+}
+
+void MacroAssembler::SubNanPreservePayloadAndSign_d(FPURegister fd,
+                                                    FPURegister fs,
+                                                    FPURegister ft) {
+  Label maybe_nan, is_nan, not_nan2008, nan2008, done;
+  Register scratch1 = t7;
+  Register scratch2 = t8;
+  Register scratch3 = t9;
+  DoubleRegister double_scratch = f8;
+
+  sub_d(fd, fs, ft);
+  // Check if the result of subtraction is NaN or infinity.
+  sub_d(double_scratch, fd, fd);
+  BranchF64(&done, nullptr, eq, double_scratch, kDoubleRegZero);
+
+  // Check if first operand is a possible NaN.
+  Mfhc1(scratch1, fs);
+  And(scratch2, scratch1, Operand(~DoubleConstants::kSignMask));
+  mfc1(scratch3, fs);
+  Branch(&is_nan, gt, scratch2, Operand(DoubleConstants::kExponentMask));
+  Branch(&maybe_nan, eq, scratch2, Operand(DoubleConstants::kExponentMask));
+  // Check if second operand is a possible NaN.
+  Mfhc1(scratch1, ft);
+  And(scratch2, scratch1, Operand(~DoubleConstants::kSignMask));
+  mfc1(scratch3, ft);
+  Branch(&is_nan, gt, scratch2, Operand(DoubleConstants::kExponentMask));
+  Branch(&done, ne, scratch2, Operand(DoubleConstants::kExponentMask));
+
+  // Check if possible NaN is actually NaN.
+  bind(&maybe_nan);
+  Branch(&done, eq, scratch3, Operand(zero_reg));
+  // If NaN is found, return it as qNaN with same payload.
+  bind(&is_nan);
+  // Determine the qNaN encoding for the current architecture.
+  LoadRoot(scratch2, Heap::kNanValueRootIndex);
+  ldc1(double_scratch, FieldMemOperand(scratch2, HeapNumber::kValueOffset));
+  Mfhc1(scratch2, double_scratch);
+  And(scratch2, scratch2, Operand(DoubleConstants::kNanTypeMask));
+  // Make NaN quiet.
+  Branch(&nan2008, gt, scratch2, Operand(zero_reg));
+  And(scratch1, scratch1, Operand(~DoubleConstants::kNanTypeMask));
+  Branch(&not_nan2008);
+  bind(&nan2008);
+  Or(scratch1, scratch1, Operand(DoubleConstants::kNanTypeMask));
+  bind(&not_nan2008);
+  mtc1(scratch3, fd);
+  Mthc1(scratch1, fd);
+  bind(&done);
+}
 
 void MacroAssembler::CompareMapAndBranch(Register obj,
                                          Register scratch,
                                          Handle<Map> map,
                                          Label* early_success,
                                          Condition cond,
                                          Label* branch_to) {
   lw(scratch, FieldMemOperand(obj, HeapObject::kMapOffset));
   CompareMapAndBranch(scratch, map, early_success, cond, branch_to);
 }
@@ skipping 2064 matching lines @@
   if (mag.shift > 0) sra(result, result, mag.shift);
   srl(at, dividend, 31);
   Addu(result, result, Operand(at));
 }
 
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_MIPS