Robustified address calculations on A64.

src/a64/simulator-a64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 789 matching lines @@
     PrintF("Hit and disabled a breakpoint at %p.\n",
            reinterpret_cast<void*>(pc_));
     Debug();
   }
 }
 
 
 void Simulator::CheckBreakNext() {
   // If the current instruction is a BL, insert a breakpoint just after it.
   if (break_on_next_ && pc_->IsBranchAndLinkToRegister()) {
-    SetBreakpoint(pc_->NextInstruction());
+    SetBreakpoint(pc_->following());
     break_on_next_ = false;
   }
 }
 
 
 void Simulator::PrintInstructionsAt(Instruction* start, uint64_t count) {
   Instruction* end = start->InstructionAtOffset(count * kInstructionSize);
-  for (Instruction* pc = start; pc < end; pc = pc->NextInstruction()) {
+  for (Instruction* pc = start; pc < end; pc = pc->following()) {
     disassembler_decoder_->Decode(pc);
   }
 }
 
 
 void Simulator::PrintSystemRegisters(bool print_all) {
   static bool first_run = true;
 
   // Define some colour codes to use for the register dump.
   // TODO(jbramley): Find a more elegant way of defining these.
@@ skipping 160 matching lines @@
     default:
       UNREACHABLE();
       break;
   }
 }
 
 
 void Simulator::VisitUnconditionalBranch(Instruction* instr) {
   switch (instr->Mask(UnconditionalBranchMask)) {
     case BL:
-      set_lr(instr->NextInstruction());
+      set_lr(instr->following());
       // Fall through.
     case B:
       set_pc(instr->ImmPCOffsetTarget());
       break;
     default:
       UNREACHABLE();
   }
 }
 
 
 void Simulator::VisitConditionalBranch(Instruction* instr) {
   ASSERT(instr->Mask(ConditionalBranchMask) == B_cond);
   if (ConditionPassed(static_cast<Condition>(instr->ConditionBranch()))) {
     set_pc(instr->ImmPCOffsetTarget());
   }
 }
 
 
 void Simulator::VisitUnconditionalBranchToRegister(Instruction* instr) {
   Instruction* target = reg<Instruction*>(instr->Rn());
   switch (instr->Mask(UnconditionalBranchToRegisterMask)) {
     case BLR: {
-      set_lr(instr->NextInstruction());
+      set_lr(instr->following());
       if (instr->Rn() == 31) {
         // BLR XZR is used as a guard for the constant pool. We should never hit
         // this, but if we do trap to allow debugging.
         Debug();
       }
       // Fall through.
     }
     case BR:
     case RET: set_pc(target); break;
     default: UNIMPLEMENTED();
@@ skipping 2322 matching lines @@
                                                           : ("");
   char const* const clr_printf        = (FLAG_log_colour) ? ("\033[0;32m")
                                                           : ("");
 
   switch (instr->Mask(ExceptionMask)) {
     case HLT: {
       if (instr->ImmException() == kImmExceptionIsDebug) {
         // Read the arguments encoded inline in the instruction stream.
         uint32_t code;
         uint32_t parameters;
-        char const * message;
 
-        ASSERT(sizeof(*pc_) == 1);
-        memcpy(&code, pc_ + kDebugCodeOffset, sizeof(code));
-        memcpy(&parameters, pc_ + kDebugParamsOffset, sizeof(parameters));
-        message = reinterpret_cast<char const *>(pc_ + kDebugMessageOffset);
+        memcpy(&code,
+               pc_->InstructionAtOffset(kDebugCodeOffset),
+               sizeof(code));
+        memcpy(&parameters,
+               pc_->InstructionAtOffset(kDebugParamsOffset),
+               sizeof(parameters));
+        char const *message =
+            reinterpret_cast<char const*>(
+                pc_->InstructionAtOffset(kDebugMessageOffset));
 
         // Always print something when we hit a debug point that breaks.
         // We are going to break, so printing something is not an issue in
         // terms of speed.
         if (FLAG_trace_sim_messages || FLAG_trace_sim || (parameters & BREAK)) {
           if (message != NULL) {
             PrintF("%sDebugger hit %d: %s%s%s\n",
                    clr_debug_number,
                    code,
                    clr_debug_message,
@@ skipping 27 matching lines @@
             // Don't print information that is already being traced.
             parameters &= ~log_parameters();
             // Print the requested information.
             if (parameters & LOG_SYS_REGS) PrintSystemRegisters(true);
             if (parameters & LOG_REGS) PrintRegisters(true);
             if (parameters & LOG_FP_REGS) PrintFPRegisters(true);
         }
 
         // The stop parameters are inlined in the code. Skip them:
         //  - Skip to the end of the message string.
-        pc_ += kDebugMessageOffset + strlen(message) + 1;
-        //  - Advance to the next aligned location.
-        pc_ = AlignUp(pc_, kInstructionSize);
+        size_t size = kDebugMessageOffset + strlen(message) + 1;
+        pc_ = pc_->InstructionAtOffset(RoundUp(size, kInstructionSize));
         //  - Verify that the unreachable marker is present.
         ASSERT(pc_->Mask(ExceptionMask) == HLT);
         ASSERT(pc_->ImmException() ==  kImmExceptionIsUnreachable);
         //  - Skip past the unreachable marker.
-        set_pc(pc_->NextInstruction());
+        set_pc(pc_->following());
 
         // Check if the debugger should break.
         if (parameters & BREAK) Debug();
 
       } else if (instr->ImmException() == kImmExceptionIsRedirectedCall) {
         // TODO(all): Extract the call redirection code into a separate
         // function.
 
         Redirection* redirection = Redirection::FromHltInstruction(instr);
 
@@ skipping 172 matching lines @@
 #endif
             break;
           }
         }
 
         set_lr(return_address);
         set_pc(return_address);
       } else if (instr->ImmException() == kImmExceptionIsPrintf) {
         // Read the argument encoded inline in the instruction stream.
         uint32_t type;
-        ASSERT(sizeof(*pc_) == 1);
-        memcpy(&type, pc_ + kPrintfTypeOffset, sizeof(type));
+        memcpy(&type,
+               pc_->InstructionAtOffset(kPrintfTypeOffset),
+               sizeof(type));
 
         const char* format = reg<const char*>(0);
 
         // Pass all of the relevant PCS registers onto printf. It doesn't
         // matter if we pass too many as the extra ones won't be read.
         int result;
         fputs(clr_printf, stream_);
         if (type == CPURegister::kRegister) {
           result = fprintf(stream_, format,
                            xreg(1), xreg(2), xreg(3), xreg(4),
@@ skipping 31 matching lines @@
     default:
       UNIMPLEMENTED();
   }
 }
 
 #endif  // USE_SIMULATOR
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_A64