Robustified address calculations on A64.

src/a64/instructions-a64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 208 matching lines @@
     ASSERT(IsLdrLiteral());
     // The offset is always shifted by 2 bits, even for loads to 64-bits
     // registers.
     offset = ImmLLiteral() << kInstructionSizeLog2;
   }
   return offset;
 }
 
 
 Instruction* Instruction::ImmPCOffsetTarget() {
-  return this + ImmPCOffset();
+  return InstructionAtOffset(ImmPCOffset());
 }
 
 
 bool Instruction::IsValidImmPCOffset(ImmBranchType branch_type,
                                      int32_t offset) {
   return is_intn(offset, ImmBranchRangeBitwidth(branch_type));
 }
 
 
 bool Instruction::IsTargetInImmPCOffsetRange(Instruction* target) {
-  int offset = target - this;
-  return IsValidImmPCOffset(BranchType(), offset);
+  return IsValidImmPCOffset(BranchType(), DistanceTo(target));
 }
 
 
 void Instruction::SetImmPCOffsetTarget(Instruction* target) {
   if (IsPCRelAddressing()) {
     SetPCRelImmTarget(target);
   } else if (BranchType() != UnknownBranchType) {
     SetBranchImmTarget(target);
   } else {
     SetImmLLiteral(target);
   }
 }
 
 
 void Instruction::SetPCRelImmTarget(Instruction* target) {
   // ADRP is not supported, so 'this' must point to an ADR instruction.
   ASSERT(Mask(PCRelAddressingMask) == ADR);
 
-  Instr imm = Assembler::ImmPCRelAddress(target - this);
+  Instr imm = Assembler::ImmPCRelAddress(DistanceTo(target));
 
   SetInstructionBits(Mask(~ImmPCRel_mask) | imm);
 }
 
 
 void Instruction::SetBranchImmTarget(Instruction* target) {
-  ASSERT(((target - this) & 3) == 0);
+  ASSERT(IsAligned(DistanceTo(target), kInstructionSize));
   Instr branch_imm = 0;
   uint32_t imm_mask = 0;
-  int offset = (target - this) >> kInstructionSizeLog2;
+  ptrdiff_t offset = DistanceTo(target) >> kInstructionSizeLog2;
   switch (BranchType()) {
     case CondBranchType: {
       branch_imm = Assembler::ImmCondBranch(offset);
       imm_mask = ImmCondBranch_mask;
       break;
     }
     case UncondBranchType: {
       branch_imm = Assembler::ImmUncondBranch(offset);
       imm_mask = ImmUncondBranch_mask;
       break;
     }
     case CompareBranchType: {
       branch_imm = Assembler::ImmCmpBranch(offset);
       imm_mask = ImmCmpBranch_mask;
       break;
     }
     case TestBranchType: {
       branch_imm = Assembler::ImmTestBranch(offset);
       imm_mask = ImmTestBranch_mask;
       break;
     }
     default: UNREACHABLE();
   }
   SetInstructionBits(Mask(~imm_mask) | branch_imm);
 }
 
 
 void Instruction::SetImmLLiteral(Instruction* source) {
-  ASSERT(((source - this) & 3) == 0);
-  int offset = (source - this) >> kLiteralEntrySizeLog2;
+  ASSERT(IsAligned(DistanceTo(source), kInstructionSize));
+  ptrdiff_t offset = DistanceTo(source) >> kLiteralEntrySizeLog2;
   Instr imm = Assembler::ImmLLiteral(offset);
   Instr mask = ImmLLiteral_mask;
 
   SetInstructionBits(Mask(~mask) | imm);
 }
 
 
 // TODO(jbramley): We can't put this inline in the class because things like
 // xzr and Register are not defined in that header. Consider adding
 // instructions-a64-inl.h to work around this.
@@ skipping 14 matching lines @@
   uint64_t payload = ImmMoveWide();
   // TODO(all): If we extend ::InlineData() to support bigger data, we need
   // to update this method too.
   return payload;
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_A64