[Subzero][MIPS32] Implement i1 cast operations

tests_lit/llvm2ice_tests/64bit.pnacl.ll

Index: tests_lit/llvm2ice_tests/64bit.pnacl.ll
diff --git a/tests_lit/llvm2ice_tests/64bit.pnacl.ll b/tests_lit/llvm2ice_tests/64bit.pnacl.ll
index aa0f26d02de6c4f17d64c2c7bb8e0f475f03026e..c0ce74798ff9d3633effe60499380fc905c0ee9a 100644
--- a/tests_lit/llvm2ice_tests/64bit.pnacl.ll
+++ b/tests_lit/llvm2ice_tests/64bit.pnacl.ll
@@ -970,6 +970,10 @@ entry:
 ; ARM32-OM1: and r0, r0, #1
 ; ARM32-O2: and r0, r0, #1
 
+; MIPS32-LABEL: trunc64To1
+; MIPS32: andi {{.*}},a0,0x1
+; MIPS32: move v0,{{.*}}
+
 define internal i64 @sext32To64(i32 %a) {
 entry:
   %conv = sext i32 %a to i64
@@ -1060,6 +1064,12 @@ entry:
 ; ARM32: mvn {{.*}}, #0
 ; ARM32: movne
 
+; MIPS32-LABEL: sext1To64
+; MIPS32: sll {{.*}},a0,0x1f
+; MIPS32: sra {{.*}},{{.*}},0x1f
+; MIPS32: move v1,{{.*}}
+; MIPS32: move v0,{{.*}}
+
 define internal i64 @zext32To64(i32 %a) {
 entry:
   %conv = zext i32 %a to i64
@@ -1145,6 +1155,11 @@ entry:
 ; ARM32: mov {{.*}}, #0
 ; ARM32: bx
 
+; MIPS32-LABEL: zext1To64
+; MIPS32: andi {{.*}},a0,0x1
+; MIPS32: li v1,0
+; MIPS32: move v0,{{.*}}
+
 define internal void @icmpEq64(i64 %a, i64 %b, i64 %c, i64 %d) {
 entry:
   %cmp = icmp eq i64 %a, %b