[Subzero][MIPS32] Implement i1 cast operations

tests_lit/llvm2ice_tests/64bit.pnacl.ll

 ; This tries to be a comprehensive test of i64 operations, in
 ; particular the patterns for lowering i64 operations into constituent
 ; i32 operations on x86-32.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \
@@ skipping 952 matching lines @@
 ;
 ; OPTM1-LABEL: trunc64To1
 ; OPTM1:      mov     eax,DWORD PTR [esp+
 ; OPTM1:      and     al,0x1
 ; OPTM1-NOT:  and     eax,0x1
 
 ; ARM32-LABEL: trunc64To1
 ; ARM32-OM1: and r0, r0, #1
 ; ARM32-O2: and r0, r0, #1
 
+; MIPS32-LABEL: trunc64To1
+; MIPS32: andi {{.*}},a0,0x1
+; MIPS32: move v0,{{.*}}
+
 define internal i64 @sext32To64(i32 %a) {
 entry:
   %conv = sext i32 %a to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: sext32To64
 ; CHECK: mov
 ; CHECK: sar {{.*}},0x1f
 ;
 ; OPTM1-LABEL: sext32To64
 ; OPTM1: mov
 ; OPTM1: sar {{.*}},0x1f
 
 ; ARM32-LABEL: sext32To64
 ; ARM32: asr {{.*}}, #31
 
 ; MIPS32-LABEL: sext32To64
-; MIPS32-LABEL: sra v1,a0,0x1f
-; MIPS32-LABEL: move v0,a0
+; MIPS32-LABEL: sra {{.*}},a0,0x1f
+; MIPS32-LABEL: move v1,{{.*}}
+; MIPS32-LABEL: move v0,{{.*}}
 
 define internal i64 @sext16To64(i32 %a) {
 entry:
   %a.arg_trunc = trunc i32 %a to i16
   %conv = sext i16 %a.arg_trunc to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: sext16To64
 ; CHECK: movsx
 ; CHECK: sar {{.*}},0x1f
 ;
 ; OPTM1-LABEL: sext16To64
 ; OPTM1: movsx
 ; OPTM1: sar {{.*}},0x1f
 
 ; ARM32-LABEL: sext16To64
 ; ARM32: sxth
 ; ARM32: asr {{.*}}, #31
 
 ; MIPS32-LABEL: sext16To64
-; MIPS32: sll a0,a0,0x10
-; MIPS32: sra a0,a0,0x10
-; MIPS32: sra v1,a0,0x1f
-; MIPS32: move v0,a0
+; MIPS32: sll {{.*}},{{.*}},0x10
+; MIPS32: sra {{.*}},{{.*}},0x10
+; MIPS32: sra {{.*}},{{.*}},0x1f
+; MIPS32: move v1,{{.*}}
+; MIPS32: move v0,{{.*}}
 
 define internal i64 @sext8To64(i32 %a) {
 entry:
   %a.arg_trunc = trunc i32 %a to i8
   %conv = sext i8 %a.arg_trunc to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: sext8To64
 ; CHECK: movsx
 ; CHECK: sar {{.*}},0x1f
 ;
 ; OPTM1-LABEL: sext8To64
 ; OPTM1: movsx
 ; OPTM1: sar {{.*}},0x1f
 
 ; ARM32-LABEL: sext8To64
 ; ARM32: sxtb
 ; ARM32: asr {{.*}}, #31
 
 ; MIPS32-LABEL: sext8To64
-; MIPS32: sll a0,a0,0x18
-; MIPS32: sra a0,a0,0x18
-; MIPS32: sra v1,a0,0x1f
-; MIPS32: move v0,a0
+; MIPS32: sll {{.*}},a0,0x18
+; MIPS32: sra {{.*}},{{.*}},0x18
+; MIPS32: sra {{.*}},{{.*}},0x1f
+; MIPS32: move v1,{{.*}}
+; MIPS32: move v0,{{.*}}
 
 define internal i64 @sext1To64(i32 %a) {
 entry:
   %a.arg_trunc = trunc i32 %a to i1
   %conv = sext i1 %a.arg_trunc to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: sext1To64
 ; CHECK: mov
 ; CHECK: shl {{.*}},0x1f
 ; CHECK: sar {{.*}},0x1f
 ;
 ; OPTM1-LABEL: sext1To64
 ; OPTM1: mov
 ; OPTM1: shl {{.*}},0x1f
 ; OPTM1: sar {{.*}},0x1f
 
 ; ARM32-LABEL: sext1To64
 ; ARM32: mov {{.*}}, #0
 ; ARM32: tst {{.*}}, #1
 ; ARM32: mvn {{.*}}, #0
 ; ARM32: movne
 
+; MIPS32-LABEL: sext1To64
+; MIPS32: sll {{.*}},a0,0x1f
+; MIPS32: sra {{.*}},{{.*}},0x1f
+; MIPS32: move v1,{{.*}}
+; MIPS32: move v0,{{.*}}
+
 define internal i64 @zext32To64(i32 %a) {
 entry:
   %conv = zext i32 %a to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: zext32To64
 ; CHECK: mov
 ; CHECK: mov {{.*}},0x0
 ;
 ; OPTM1-LABEL: zext32To64
 ; OPTM1: mov
 ; OPTM1: mov {{.*}},0x0
 
 ; ARM32-LABEL: zext32To64
 ; ARM32: mov {{.*}}, #0
 
 ; MIPS32-LABEL: zext32To64
-; MIPS32: li v1,0
-; MIPS32: move v0,a0
+; MIPS32: li {{.*}},0
+; MIPS32: move v1,{{.*}}
+; MIPS32: move v0,{{.*}}
 
 define internal i64 @zext16To64(i32 %a) {
 entry:
   %a.arg_trunc = trunc i32 %a to i16
   %conv = zext i16 %a.arg_trunc to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: zext16To64
 ; CHECK: movzx
 ; CHECK: mov {{.*}},0x0
 ;
 ; OPTM1-LABEL: zext16To64
 ; OPTM1: movzx
 ; OPTM1: mov {{.*}},0x0
 
 ; ARM32-LABEL: zext16To64
 ; ARM32: uxth
 ; ARM32: mov {{.*}}, #0
 
 ; MIPS32-LABEL: zext16To64
-; MIPS32: andi a0,a0,0xffff
-; MIPS32: li v1,0
-; MIPS32: move v0,a0
+; MIPS32: andi {{.*}},a0,0xffff
+; MIPS32: li {{.*}},0
+; MIPS32: move v1,{{.*}}
+; MIPS32: move v0,{{.*}}
 
 define internal i64 @zext8To64(i32 %a) {
 entry:
   %a.arg_trunc = trunc i32 %a to i8
   %conv = zext i8 %a.arg_trunc to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: zext8To64
 ; CHECK: movzx
 ; CHECK: mov {{.*}},0x0
 ;
 ; OPTM1-LABEL: zext8To64
 ; OPTM1: movzx
 ; OPTM1: mov {{.*}},0x0
 
 ; ARM32-LABEL: zext8To64
 ; ARM32: uxtb
 ; ARM32: mov {{.*}}, #0
 
 ; MIPS32-LABEL: zext8To64
-; MIPS32: andi a0,a0,0xff
-; MIPS32: li v1,0
-; MIPS32: move v0,a0
+; MIPS32: andi {{.*}},a0,0xff
+; MIPS32: li {{.*}},0
+; MIPS32: move v1,{{.*}}
+; MIPS32: move v0,{{.*}}
 
 define internal i64 @zext1To64(i32 %a) {
 entry:
   %a.arg_trunc = trunc i32 %a to i1
   %conv = zext i1 %a.arg_trunc to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: zext1To64
 ; CHECK: and {{.*}},0x1
 ; CHECK: mov {{.*}},0x0
 ;
 ; OPTM1-LABEL: zext1To64
 ; OPTM1: and {{.*}},0x1
 ; OPTM1: mov {{.*}},0x0
 
 ; ARM32-LABEL: zext1To64
 ; ARM32: and {{.*}}, #1
 ; ARM32: mov {{.*}}, #0
 ; ARM32: bx
 
+; MIPS32-LABEL: zext1To64
+; MIPS32: andi {{.*}},a0,0x1
+; MIPS32: li {{.*}},0
+; MIPS32: move v1,{{.*}}
+; MIPS32: move v0,{{.*}}
+
 define internal void @icmpEq64(i64 %a, i64 %b, i64 %c, i64 %d) {
 entry:
   %cmp = icmp eq i64 %a, %b
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   call void @func()
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
@@ skipping 879 matching lines @@
   %s = lshr i64 %a, 40
   %t = trunc i64 %s to i32
   %r = sub i32 %t, 1
   ret i32 %r
 ; ARM32-LABEL: subOneToUpperAfterShift
 ; ARM32: subs
 ; ARM32: sbc
 ; ARM32: lsr
 ; ARM32: sub
 }