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Side by Side Diff: test/unittests/compiler/arm64/instruction-selector-arm64-unittest.cc

Issue 2011303002: [arm] [arm64] Add optional operators Float32Neg and Float64Neg. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 4 years, 6 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "test/unittests/compiler/instruction-selector-unittest.h" 5 #include "test/unittests/compiler/instruction-selector-unittest.h"
6 6
7 namespace v8 { 7 namespace v8 {
8 namespace internal { 8 namespace internal {
9 namespace compiler { 9 namespace compiler {
10 10
(...skipping 3556 matching lines...) Expand 10 before | Expand all | Expand 10 after
3567 // Float64Min is `(a < b) ? a : b`. 3567 // Float64Min is `(a < b) ? a : b`.
3568 ASSERT_EQ(1U, s.size()); 3568 ASSERT_EQ(1U, s.size());
3569 EXPECT_EQ(kArm64Float64Min, s[0]->arch_opcode()); 3569 EXPECT_EQ(kArm64Float64Min, s[0]->arch_opcode());
3570 ASSERT_EQ(2U, s[0]->InputCount()); 3570 ASSERT_EQ(2U, s[0]->InputCount());
3571 EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0))); 3571 EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
3572 EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1))); 3572 EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
3573 ASSERT_EQ(1U, s[0]->OutputCount()); 3573 ASSERT_EQ(1U, s[0]->OutputCount());
3574 EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); 3574 EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
3575 } 3575 }
3576 3576
3577 TEST_F(InstructionSelectorTest, Float32Neg) {
3578 StreamBuilder m(this, MachineType::Float32(), MachineType::Float32());
3579 Node* const p0 = m.Parameter(0);
3580 // Don't use m.Float32Neg() as that generates an explicit sub.
3581 Node* const n = m.AddNode(m.machine()->Float32Neg().op(), m.Parameter(0));
3582 m.Return(n);
3583 Stream s = m.Build();
3584 ASSERT_EQ(1U, s.size());
3585 EXPECT_EQ(kArm64Float32Neg, s[0]->arch_opcode());
3586 ASSERT_EQ(1U, s[0]->InputCount());
3587 EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
3588 ASSERT_EQ(1U, s[0]->OutputCount());
3589 EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
3590 }
3591
3592 TEST_F(InstructionSelectorTest, Float64Neg) {
3593 StreamBuilder m(this, MachineType::Float64(), MachineType::Float64());
3594 Node* const p0 = m.Parameter(0);
3595 // Don't use m.Float64Neg() as that generates an explicit sub.
3596 Node* const n = m.AddNode(m.machine()->Float64Neg().op(), m.Parameter(0));
3597 m.Return(n);
3598 Stream s = m.Build();
3599 ASSERT_EQ(1U, s.size());
3600 EXPECT_EQ(kArm64Float64Neg, s[0]->arch_opcode());
3601 ASSERT_EQ(1U, s[0]->InputCount());
3602 EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
3603 ASSERT_EQ(1U, s[0]->OutputCount());
3604 EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
3605 }
3606
3577 } // namespace compiler 3607 } // namespace compiler
3578 } // namespace internal 3608 } // namespace internal
3579 } // namespace v8 3609 } // namespace v8
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