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Side by Side Diff: test/unittests/compiler/arm/instruction-selector-arm-unittest.cc

Issue 2011303002: [arm] [arm64] Add optional operators Float32Neg and Float64Neg. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 4 years, 6 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include <limits> 5 #include <limits>
6 6
7 #include "test/unittests/compiler/instruction-selector-unittest.h" 7 #include "test/unittests/compiler/instruction-selector-unittest.h"
8 8
9 namespace v8 { 9 namespace v8 {
10 namespace internal { 10 namespace internal {
(...skipping 3041 matching lines...) Expand 10 before | Expand all | Expand 10 after
3052 // Float64Min is `(a < b) ? a : b`. 3052 // Float64Min is `(a < b) ? a : b`.
3053 ASSERT_EQ(1U, s.size()); 3053 ASSERT_EQ(1U, s.size());
3054 EXPECT_EQ(kArmFloat64Min, s[0]->arch_opcode()); 3054 EXPECT_EQ(kArmFloat64Min, s[0]->arch_opcode());
3055 ASSERT_EQ(2U, s[0]->InputCount()); 3055 ASSERT_EQ(2U, s[0]->InputCount());
3056 EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0))); 3056 EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
3057 EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1))); 3057 EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
3058 ASSERT_EQ(1U, s[0]->OutputCount()); 3058 ASSERT_EQ(1U, s[0]->OutputCount());
3059 EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); 3059 EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
3060 } 3060 }
3061 3061
3062 TEST_F(InstructionSelectorTest, Float32Neg) {
3063 StreamBuilder m(this, MachineType::Float32(), MachineType::Float32());
3064 Node* const p0 = m.Parameter(0);
3065 // Don't use m.Float32Neg() as that generates an explicit sub.
3066 Node* const n = m.AddNode(m.machine()->Float32Neg().op(), m.Parameter(0));
3067 m.Return(n);
3068 Stream s = m.Build();
3069 ASSERT_EQ(1U, s.size());
3070 EXPECT_EQ(kArmVnegF32, s[0]->arch_opcode());
3071 ASSERT_EQ(1U, s[0]->InputCount());
3072 EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
3073 ASSERT_EQ(1U, s[0]->OutputCount());
3074 EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
3075 }
3076
3077 TEST_F(InstructionSelectorTest, Float64Neg) {
3078 StreamBuilder m(this, MachineType::Float64(), MachineType::Float64());
3079 Node* const p0 = m.Parameter(0);
3080 // Don't use m.Float64Neg() as that generates an explicit sub.
3081 Node* const n = m.AddNode(m.machine()->Float64Neg().op(), m.Parameter(0));
3082 m.Return(n);
3083 Stream s = m.Build();
3084 ASSERT_EQ(1U, s.size());
3085 EXPECT_EQ(kArmVnegF64, s[0]->arch_opcode());
3086 ASSERT_EQ(1U, s[0]->InputCount());
3087 EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
3088 ASSERT_EQ(1U, s[0]->OutputCount());
3089 EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
3090 }
3091
3062 } // namespace compiler 3092 } // namespace compiler
3063 } // namespace internal 3093 } // namespace internal
3064 } // namespace v8 3094 } // namespace v8
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