Implement ldrex and strex in ARM simulator

src/arm/simulator-arm.h

Index: src/arm/simulator-arm.h
diff --git a/src/arm/simulator-arm.h b/src/arm/simulator-arm.h
index b3c8eb41e515ba911183e452a3116f6e87094efd..6b568abdc71f018f013079beae8714b62d1da76d 100644
--- a/src/arm/simulator-arm.h
+++ b/src/arm/simulator-arm.h
@@ -14,6 +14,8 @@
 #define V8_ARM_SIMULATOR_ARM_H_
 
 #include "src/allocation.h"
+#include "src/base/lazy-instance.h"
+#include "src/base/platform/mutex.h"
 
 #if !defined(USE_SIMULATOR)
 // Running without a simulator on a native arm platform.
@@ -429,6 +431,64 @@ class Simulator {
     char* desc;
   };
   StopCountAndDesc watched_stops_[kNumOfWatchedStops];
+
+  // Syncronization primitives. See ARM DDI 0406C.b, A2.9.
+  class DataMonitor {
+   public:
+    DataMonitor();
+
+    // Read and write exclusive. The writes return the strex status: 0 if the
+    // write succeeds, and 1 if the write fails.
+    uint8_t ReadExBU(Simulator* simulator, int32_t addr);
+    int WriteExB(Simulator* simulator,
+                 int32_t addr,
+                 uint8_t value);
+
+    uint16_t ReadExHU(Simulator* simulator, int32_t addr, Instruction* instr);
+    int WriteExH(Simulator* simulator,
+                 int32_t addr,
+                 uint16_t value,
+                 Instruction* instr);
+
+    int ReadExW(Simulator* simulator, int32_t addr, Instruction* instr);
+    int WriteExW(Simulator* simulator,
+                 int32_t addr,
+                 int value,
+                 Instruction* instr);
+
+   private:
+    // Common code for exclusive loads/stores. WriteExInternal returns true if
+    // the write will succeed.
+    void ReadExInternal_Locked(int32_t addr);
+    bool WriteExInternal_Locked(int32_t addr);
+
+    void RemoveNode_Locked();
+    void PrependNode_Locked();
+    DataMonitor* FirstNodeWithTaggedAddr_Locked(int32_t addr);
+
+    // The exclusive range of a tagged address has an implementation defined
+    // size, with a minimum size of the access size, and a maximum size of 128
+    // bytes.
+    static const int32_t kAddrMask = ~7;
+
+    enum class Access {
+      Open,
+      Exclusive,
+    };
+
+    static base::LazyMutex mutex_;
+
+    Access access_state_;
+    int32_t tagged_addr_;
+
+    // An Isolate's DataMonitor is only in this linked list if it currently has
+    // exclusive access for some address range.

[jbramley, 2016/05/31 16:58:47]

The global monitor remembers a single outstanding exclusive access per core,
along with its associated state machine. Rather than use a linked list, it would
probably be simpler to use a simple vector, with one element per simulated core.

[binji, 2016/06/01 21:06:40]

I was writing this as though each Simulator is one core. It's a bit strange, but
it matches the way the things are currently generated: if you create two
Workers, you get two Isolates, which gives you two Simulators.

+    static DataMonitor* head_;

[jbramley, 2016/05/31 16:58:47]

I can't see how the list is allocated. Does this currently only support a single
thread?

[binji, 2016/06/01 21:06:40]

Each DataMonitor is a node in the list, so it is allocated along with the
Simulator (and Isolate). This matches the Worker model which we're trying to
emulate for the Atomics API.

+    DataMonitor* next_;
+    DataMonitor* prev_;
+  };
+
+  DataMonitor data_monitor_;
 };