Implement ldrex and strex in ARM simulator

src/arm/simulator-arm.h

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 
 // Declares a Simulator for ARM instructions if we are not generating a native
 // ARM binary. This Simulator allows us to run and debug ARM code generation on
 // regular desktop machines.
 // V8 calls into generated code by "calling" the CALL_GENERATED_CODE macro,
 // which will start execution in the Simulator or forwards to the real entry
 // on a ARM HW platform.
 
 #ifndef V8_ARM_SIMULATOR_ARM_H_
 #define V8_ARM_SIMULATOR_ARM_H_
 
 #include "src/allocation.h"
+#include "src/base/lazy-instance.h"
+#include "src/base/platform/mutex.h"
 
 #if !defined(USE_SIMULATOR)
 // Running without a simulator on a native arm platform.
 
 namespace v8 {
 namespace internal {
 
 // When running without a simulator we call the entry directly.
 #define CALL_GENERATED_CODE(isolate, entry, p0, p1, p2, p3, p4) \
   (entry(p0, p1, p2, p3, p4))
@@ skipping 395 matching lines @@
 
   // A stop is enabled, meaning the simulator will stop when meeting the
   // instruction, if bit 31 of watched_stops_[code].count is unset.
   // The value watched_stops_[code].count & ~(1 << 31) indicates how many times
   // the breakpoint was hit or gone through.
   struct StopCountAndDesc {
     uint32_t count;
     char* desc;
   };
   StopCountAndDesc watched_stops_[kNumOfWatchedStops];
+
+  // Syncronization primitives. See ARM DDI 0406C.b, A2.9.
+  class DataMonitor {
+   public:
+    DataMonitor();
+
+    // Read and write exclusive. The writes return the strex status: 0 if the
+    // write succeeds, and 1 if the write fails.
+    uint8_t ReadExBU(Simulator* simulator, int32_t addr);
+    int WriteExB(Simulator* simulator,
+                 int32_t addr,
+                 uint8_t value);
+
+    uint16_t ReadExHU(Simulator* simulator, int32_t addr, Instruction* instr);
+    int WriteExH(Simulator* simulator,
+                 int32_t addr,
+                 uint16_t value,
+                 Instruction* instr);
+
+    int ReadExW(Simulator* simulator, int32_t addr, Instruction* instr);
+    int WriteExW(Simulator* simulator,
+                 int32_t addr,
+                 int value,
+                 Instruction* instr);
+
+   private:
+    // Common code for exclusive loads/stores. WriteExInternal returns true if
+    // the write will succeed.
+    void ReadExInternal_Locked(int32_t addr);
+    bool WriteExInternal_Locked(int32_t addr);
+
+    void RemoveNode_Locked();
+    void PrependNode_Locked();
+    DataMonitor* FirstNodeWithTaggedAddr_Locked(int32_t addr);
+
+    // The exclusive range of a tagged address has an implementation defined
+    // size, with a minimum size of the access size, and a maximum size of 128
+    // bytes.
+    static const int32_t kAddrMask = ~7;
+
+    enum class Access {
+      Open,
+      Exclusive,
+    };
+
+    static base::LazyMutex mutex_;
+
+    Access access_state_;
+    int32_t tagged_addr_;
+
+    // An Isolate's DataMonitor is only in this linked list if it currently has
+    // exclusive access for some address range.

[jbramley, 2016/05/31 16:58:47]

The global monitor remembers a single outstanding exclusive access per core,
along with its associated state machine. Rather than use a linked list, it would
probably be simpler to use a simple vector, with one element per simulated core.

[binji, 2016/06/01 21:06:40]

I was writing this as though each Simulator is one core. It's a bit strange, but
it matches the way the things are currently generated: if you create two
Workers, you get two Isolates, which gives you two Simulators.

+    static DataMonitor* head_;

[jbramley, 2016/05/31 16:58:47]

I can't see how the list is allocated. Does this currently only support a single
thread?

[binji, 2016/06/01 21:06:40]

Each DataMonitor is a node in the list, so it is allocated along with the
Simulator (and Isolate). This matches the Worker model which we're trying to
emulate for the Atomics API.

+    DataMonitor* next_;
+    DataMonitor* prev_;
+  };
+
+  DataMonitor data_monitor_;
 };
 
 
 // When running with the simulator transition into simulated execution at this
 // point.
 #define CALL_GENERATED_CODE(isolate, entry, p0, p1, p2, p3, p4) \
   reinterpret_cast<Object*>(Simulator::current(isolate)->Call(  \
       FUNCTION_ADDR(entry), 5, p0, p1, p2, p3, p4))
 
 #define CALL_GENERATED_FP_INT(isolate, entry, p0, p1) \
@@ skipping 25 matching lines @@
   static inline void UnregisterCTryCatch(v8::internal::Isolate* isolate) {
     Simulator::current(isolate)->PopAddress();
   }
 };
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // !defined(USE_SIMULATOR)
 #endif  // V8_ARM_SIMULATOR_ARM_H_