tests_lit/llvm2ice_tests/store.ll - Issue 2005823002: [Subzero][MIPS32] Add LowerStore implementation

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Issue 2005823002: [Subzero][MIPS32] Add LowerStore implementation (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master

Patch Set: Addressed review comments, enabled store test for MIPS32 Created 4 years, 6 months ago

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1 ; Simple test of the store instruction.	1 ; Simple test of the store instruction.

2	2

3 ; REQUIRES: allow_dump	3 ; REQUIRES: allow_dump

4	4

5 ; RUN: %p2i -i %s --args --verbose inst -threads=0 \| FileCheck %s	5 ; RUN: %p2i -i %s --args --verbose inst -threads=0 \| FileCheck %s

6	6

	7 ; RUN: %if --need=target_MIPS32 --need=allow_dump \

	8 ; RUN: --command %p2i --filetype=asm --assemble \

	9 ; RUN: --disassemble --target mips32 -i %s --args -O2 --skip-unimplemented \

	10 ; RUN: -allow-externally-defined-symbols \

	11 ; RUN: \| %if --need=target_MIPS32 --need=allow_dump \

	12 ; RUN: --command FileCheck --check-prefix MIPS32 %s

	13

7 define internal void @store_i64(i32 %addr_arg) {	14 define internal void @store_i64(i32 %addr_arg) {

8 entry:	15 entry:

9 %__1 = inttoptr i32 %addr_arg to i64*	16 %__1 = inttoptr i32 %addr_arg to i64*

10 store i64 1, i64* %__1, align 1	17 store i64 1, i64* %__1, align 1

11 ret void	18 ret void

12	19

13 ; CHECK: Initial CFG	20 ; CHECK: Initial CFG

14 ; CHECK: entry:	21 ; CHECK: entry:

15 ; CHECK-NEXT: store i64 1, i64* %addr_arg, align 1	22 ; CHECK-NEXT: store i64 1, i64* %addr_arg, align 1

16 ; CHECK-NEXT: ret void	23 ; CHECK-NEXT: ret void

17 }	24 }

	25 ; MIPS32-LABEL: store_i64

	26 ; MIPS32: li

	27 ; MIPS32: li

	28 ; MIPS32: sw

	29 ; MIPS32: sw

18	30

19 define internal void @store_i32(i32 %addr_arg) {	31 define internal void @store_i32(i32 %addr_arg) {

20 entry:	32 entry:

21 %__1 = inttoptr i32 %addr_arg to i32*	33 %__1 = inttoptr i32 %addr_arg to i32*

22 store i32 1, i32* %__1, align 1	34 store i32 1, i32* %__1, align 1

23 ret void	35 ret void

24	36

25 ; CHECK: Initial CFG	37 ; CHECK: Initial CFG

26 ; CHECK: entry:	38 ; CHECK: entry:

27 ; CHECK-NEXT: store i32 1, i32* %addr_arg, align 1	39 ; CHECK-NEXT: store i32 1, i32* %addr_arg, align 1

28 ; CHECK-NEXT: ret void	40 ; CHECK-NEXT: ret void

29 }	41 }

	42 ; MIPS32-LABEL: store_i32

	43 ; MIPS32: li

	44 ; MIPS32: sw

30	45

31 define internal void @store_i16(i32 %addr_arg) {	46 define internal void @store_i16(i32 %addr_arg) {

32 entry:	47 entry:

33 %__1 = inttoptr i32 %addr_arg to i16*	48 %__1 = inttoptr i32 %addr_arg to i16*

34 store i16 1, i16* %__1, align 1	49 store i16 1, i16* %__1, align 1

35 ret void	50 ret void

36	51

37 ; CHECK: Initial CFG	52 ; CHECK: Initial CFG

38 ; CHECK: entry:	53 ; CHECK: entry:

39 ; CHECK-NEXT: store i16 1, i16* %addr_arg, align 1	54 ; CHECK-NEXT: store i16 1, i16* %addr_arg, align 1

40 ; CHECK-NEXT: ret void	55 ; CHECK-NEXT: ret void

41 }	56 }

	57 ; MIPS32-LABEL: store_i16

	58 ; MIPS32: li

	59 ; MIPS32: sw

42	60

43 define internal void @store_i8(i32 %addr_arg) {	61 define internal void @store_i8(i32 %addr_arg) {

44 entry:	62 entry:

45 %__1 = inttoptr i32 %addr_arg to i8*	63 %__1 = inttoptr i32 %addr_arg to i8*

46 store i8 1, i8* %__1, align 1	64 store i8 1, i8* %__1, align 1

47 ret void	65 ret void

48	66

49 ; CHECK: Initial CFG	67 ; CHECK: Initial CFG

50 ; CHECK: entry:	68 ; CHECK: entry:

51 ; CHECK-NEXT: store i8 1, i8* %addr_arg, align 1	69 ; CHECK-NEXT: store i8 1, i8* %addr_arg, align 1

52 ; CHECK-NEXT: ret void	70 ; CHECK-NEXT: ret void

53 }	71 }

	72 ; MIPS32-LABEL: store_i8

	73 ; MIPS32: li

	74 ; MIPS32: sw

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